arxiv: 2604.09956 · v1 · submitted 2026-04-10 · 🪐 quant-ph

Recognition: unknown

Logical Compilation for Multi-Qubit Iceberg Patches

Cordell Mazzetti, Jonathan Mark Baker, Pranav Gokhale, Rich Rines, Sayam Sethi

Pith reviewed 2026-05-10 16:42 UTC · model grok-4.3

classification 🪐 quant-ph

keywords quantum compilationiceberg codehigh-rate error correctionqubit mappinggate merginglogical qubitscircuit optimizationquantum error detection

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The pith

A new compiler optimizes qubit mappings and merges gates for high-rate Iceberg codes to cut circuit depth by 34%.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper addresses the challenge of compiling quantum circuits onto high-rate error-detecting codes such as Iceberg patches, which encode multiple logical qubits per physical block and therefore require careful assignment of program qubits to logical positions to avoid correlated errors. It introduces a two-part framework that first converts logical gates into physical operations through Hadamard commutation and gate merging, then applies a fast heuristic to search over possible mappings. This avoids the exponential cost of exhaustive enumeration while producing shallower, lower-error circuits. Results on 71 benchmark circuits demonstrate consistent gains over naive mapping strategies.

Core claim

The paper claims that pairing logical-to-physical compilation via Hadamard commutation and gate merging with a merge-optimizing, noise-biased packing heuristic for qubit-to-logical assignment enables practical compilation for multi-qubit Iceberg patches. Across 71 benchmark circuits this yields a 34% average reduction in circuit depth, reductions of up to 31% in one-qubit gates and 17% in two-qubit gates, a 1.75 times improvement in total variation distance, and an 86% average improvement in logical selection rate relative to naive compilation.

What carries the argument

The merge-optimizing, noise-biased packing heuristic that selects qubit-to-logical mappings, supported by Hadamard commutation and gate merging during logical-to-physical translation.

If this is right

Circuit depth falls by 34% on average across standard benchmarks.
One-qubit gate counts decrease by as much as 31%.
Two-qubit gate counts decrease by 17%.
Total variation distance improves by a factor of 1.75.
Logical selection rate rises by 86% on average.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

The same heuristic search could be applied to other high-rate codes that place multiple logical qubits inside a single patch.
The mapping step could be inserted into existing compilation pipelines that already perform routing or scheduling.
Higher logical selection rates open the possibility of runtime remapping when circuit structure changes mid-execution.

Load-bearing premise

The merge-optimizing, noise-biased packing heuristic reliably identifies high-performing qubit assignments for practical circuits without exhaustive search.

What would settle it

Enumerating all mappings on small benchmark circuits and checking whether the heuristic consistently returns assignments whose fidelity lies within a few percent of the best possible mapping would directly test the claim.

Figures

Figures reproduced from arXiv: 2604.09956 by Cordell Mazzetti, Jonathan Mark Baker, Pranav Gokhale, Rich Rines, Sayam Sethi.

**Figure 2.** Figure 2: Comparison of a trivial and optimized permutation [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗

**Figure 4.** Figure 4: Differences between Hadamard and controlled-X [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗

**Figure 3.** Figure 3: Physical encoding and decoding circuit for a sin [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗

**Figure 5.** Figure 5: Logical fidelities of different CNOT implementa [PITH_FULL_IMAGE:figures/full_fig_p004_5.png] view at source ↗

**Figure 6.** Figure 6: Overview of the gate merging algorithm. The algorithm runs in [PITH_FULL_IMAGE:figures/full_fig_p005_6.png] view at source ↗

**Figure 7.** Figure 7: Commuting Hadamards through a small circuit. [PITH_FULL_IMAGE:figures/full_fig_p005_7.png] view at source ↗

**Figure 8.** Figure 8: Greedy assignment of qubit pairs from the score [PITH_FULL_IMAGE:figures/full_fig_p006_8.png] view at source ↗

**Figure 9.** Figure 9: Compilation pipeline for an example logical circuit. (1a) Gate cancellation, (1b) Hadamard commutation, (1c) second [PITH_FULL_IMAGE:figures/full_fig_p008_9.png] view at source ↗

**Figure 10.** Figure 10: Our framework enables significant resource reduction for 71 QASMBench circuits. Across these benchmarks, our [PITH_FULL_IMAGE:figures/full_fig_p009_10.png] view at source ↗

**Figure 11.** Figure 11: Packing and merging improvement over random permutations by packing density. Each point compares our [PITH_FULL_IMAGE:figures/full_fig_p010_11.png] view at source ↗

**Figure 12.** Figure 12: Compilation techniques significantly improve re [PITH_FULL_IMAGE:figures/full_fig_p011_12.png] view at source ↗

**Figure 13.** Figure 13: Ablation of techniques over packing density. [PITH_FULL_IMAGE:figures/full_fig_p011_13.png] view at source ↗

**Figure 14.** Figure 14: Single qubit gate operations and swap Columns [PITH_FULL_IMAGE:figures/full_fig_p013_14.png] view at source ↗

**Figure 15.** Figure 15: CX, CZ, and XCX gate operations. The first column is the program circuit. The second column is the intra-patch [PITH_FULL_IMAGE:figures/full_fig_p014_15.png] view at source ↗

**Figure 16.** Figure 16: Encoded Hadamard operations. be seen in Figure 17b with post-selection acting as an exponentially strict filter [PITH_FULL_IMAGE:figures/full_fig_p014_16.png] view at source ↗

**Figure 17.** Figure 17: Logical selection rate and total variation distance are strongly anticorrelated across parameter regimes. Each subplot [PITH_FULL_IMAGE:figures/full_fig_p015_17.png] view at source ↗

read the original abstract

Recent advancements in quantum computing have enabled practical use of quantum error detecting and correcting codes. However, current architectures and future proposals of quantum computer design suffer from limited qubit counts, necessitating the use of high-rate codes. Such codes, with their code parameters denoted as $[[n, k, d]]$, have more than $1$ logical qubit per code (i.e., $k > 1$). This leads to reduced error tolerance of the code, since $\lceil (d-1)/2\rceil$ errors on any of the $n$ physical qubits can affect the logical state of all $k$ logical qubits. Therefore, it becomes critical to optimally map the input qubits of a quantum circuit to these codes, in such a way that the circuit fidelity is maximized. \par However, the problem of mapping program qubits to logical qubits for high-rate codes has not been studied in prior work. A brute force search to find the optimal mapping is super exponential (scaling as $O(n!)$, where $n$ is the number of input qubits), making exhaustive search infeasible past a small number of qubits. We propose a framework that addresses this problem on two fronts: (1) for any given mapping, it performs logical-to-physical compilation that translates input gates into efficiently encoded implementations utilizing Hadamard commutation and gate merging; and (2) it quickly searches the space of possible mappings through a merge-optimizing, noise-biased packing heuristic that identifies high-performing qubit assignments without exhaustive enumeration. To the best of our knowledge, our compiler is the first work to explore mapping and compilation for high-rate codes. Across 71 benchmark circuits, we reduce circuit depth by $34\%$, gate counts by up to $31\%$ and $17\%$ for one-qubit and two-qubit gates, and improve total variation distance by $1.75\times$, with logical selection rate improvements averaging $86\%$ relative to naive compilation.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

The paper gives the first heuristic compiler for mapping circuits to high-rate Iceberg codes, with benchmark gains, but skips direct checks against optimal mappings on small instances.

read the letter

The core of this work is a two-part framework for high-rate codes: a logical-to-physical compilation step that uses Hadamard commutation to merge gates, plus a merge-optimizing noise-biased packing heuristic to pick qubit assignments. The abstract positions this as the first treatment of the mapping problem for these codes, which is a fair claim given the prior focus on distance-3 or lower-rate patches. The reported results on 71 circuits—34% depth cut, up to 31% and 17% gate reductions, 1.75× better TVD, and 86% average lift in logical selection rate—give a concrete sense of the payoff over naive assignment. That practical angle on limited-qubit hardware is the strongest part; it directly targets a constraint that matters for near-term code use. The heuristic itself is a reasonable engineering choice to sidestep O(n!) search. The main gap is the one flagged in the stress test. The paper does not show how the heuristic performs against exhaustive enumeration on circuits with 6 or fewer program qubits, where optimal mappings can be computed exactly. Without that anchor, it is difficult to judge whether the gains are close to the best possible or simply better than an unspecified naive baseline. The noise-bias weight is also a tunable parameter whose effect on the outcomes is not explored in the abstract. This work is aimed at quantum compilation and error-correction researchers who need to place circuits onto multi-logical-qubit patches. A reader already working on Iceberg or similar high-rate codes will pick up usable ideas from the commutation and packing steps. It is solid enough on novelty and relevance to merit a serious referee, though the evaluation would benefit from the small-n optimality checks and clearer baseline definitions. I would send it out for review with those requests.

Referee Report

1 major / 2 minor

Summary. The manuscript proposes a two-part framework for compiling quantum circuits to high-rate error-detecting codes (e.g., Iceberg patches [[n,k,d]] with k>1). Part (1) performs logical-to-physical compilation via Hadamard commutation and gate merging to produce efficient encoded implementations. Part (2) searches the mapping space with a merge-optimizing, noise-biased packing heuristic that avoids O(n!) exhaustive enumeration. On 71 benchmark circuits the authors report 34% depth reduction, up to 31%/17% reductions in 1Q/2Q gate counts, 1.75× TVD improvement, and 86% average logical-selection-rate gain versus naive compilation.

Significance. If the heuristic is shown to be reliable, the work would be significant as the first systematic treatment of mapping and compilation for high-rate codes, directly addressing the tension between limited physical qubit counts and the need for k>1 logical qubits. The concrete benchmark gains and the explicit separation of compilation from mapping search provide a practical path toward higher-fidelity execution on near-term hardware.

major comments (1)

[§5 (Evaluation)] §5 (Evaluation): The headline performance numbers (34% depth, 31%/17% gate-count, 1.75× TVD, 86% selection-rate gains) are generated exclusively by the merge-optimizing noise-biased packing heuristic. No comparison against the exact optimum is supplied for any circuit with ≤6 program qubits, where brute-force enumeration of all mappings is computationally feasible. Because the central claim is that the heuristic reliably identifies high-performing assignments, the absence of this sanity check leaves open the possibility that the reported advantage over the (unspecified) naive baseline is smaller than claimed or even absent on some instances.

minor comments (2)

[Abstract and §3] Abstract and §3: the baseline labeled 'naive compilation' is never defined; the reader cannot determine whether it corresponds to random mapping, identity mapping, or some other standard procedure.
[Abstract] Abstract: the statement 'super exponential (scaling as O(n!))' is imprecise; factorial growth is exponential in n log n. A brief clarification of the precise complexity would aid readability.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for their constructive feedback. We address the major comment below and will revise the manuscript to strengthen the evaluation as indicated.

read point-by-point responses

Referee: The headline performance numbers (34% depth, 31%/17% gate-count, 1.75× TVD, 86% selection-rate gains) are generated exclusively by the merge-optimizing noise-biased packing heuristic. No comparison against the exact optimum is supplied for any circuit with ≤6 program qubits, where brute-force enumeration of all mappings is computationally feasible. Because the central claim is that the heuristic reliably identifies high-performing assignments, the absence of this sanity check leaves open the possibility that the reported advantage over the (unspecified) naive baseline is smaller than claimed or even absent on some instances.

Authors: We agree that a direct comparison of the heuristic to the exact optimal mapping for circuits with ≤6 program qubits would provide valuable validation of its reliability. While the manuscript emphasizes results on larger benchmarks where exhaustive search is intractable, we acknowledge that including this sanity check for small instances would address the concern about the magnitude of improvement over the naive baseline. In the revised manuscript, we will add a new subsection to §5 that enumerates all mappings for every benchmark circuit with up to 6 program qubits, reports the optimality gap of the heuristic, and confirms that it consistently identifies high-performing assignments. revision: yes

Circularity Check

0 steps flagged

No circularity: empirical evaluation of independent heuristic against naive baseline

full rationale

The paper defines a merge-optimizing noise-biased packing heuristic and a logical-to-physical compilation procedure, then reports empirical improvements on 71 external benchmark circuits relative to an unspecified naive baseline. No equations, parameters, or results are shown to reduce by construction to the inputs (no fitted-input-called-prediction, no self-definitional mapping, no load-bearing self-citation chain). The central claims remain independent of the reported numbers.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

Based solely on the abstract; the compilation step assumes standard properties of quantum gates while the search step introduces at least one tunable bias parameter whose value is not specified.

free parameters (1)

noise bias weight
Controls how strongly the packing heuristic favors mappings that protect noise-sensitive operations; value not reported in abstract.

axioms (1)

domain assumption Hadamard commutation and gate merging preserve correctness when translating gates into the encoded patch.
Invoked in the logical-to-physical compilation component described in the abstract.

pith-pipeline@v0.9.0 · 5672 in / 1294 out tokens · 65323 ms · 2026-05-10T16:42:54.593677+00:00 · methodology

discussion (0)

Reference graph

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