arxiv: 2604.15436 · v1 · submitted 2026-04-16 · 🪐 quant-ph

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Parity-unfolded distillation architecture for noise-biased platforms

Konstantin Tiurev , Christoph Fleckenstein , Christophe Goeller , Paul Schnabl , Matthias Traube , Nitica Sakharwade , Anette Messinger , Josua Unger

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Wolfgang Lechner

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Pith reviewed 2026-05-10 10:42 UTC · model grok-4.3

classification 🪐 quant-ph

keywords fault-tolerant quantum computingmagic state distillationClifford hierarchybiased noisesmall-angle rotationsquantum Fourier transformresource overhead

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The pith

Parity-unfolded distillation prepares small-angle rotations directly on noise-biased platforms with 26% lower resources.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces a parity-unfolded architecture for fault-tolerant quantum computation that prepares small-angle rotation gates directly by distilling states from any level of the Clifford hierarchy. This avoids the usual approximation with Clifford plus T gates and takes advantage of noise bias in the hardware. A state for rotation by one over two to the k can be made using two to the k plus three plus order two to the k over two biased-noise qubits arranged on a planar chip with only nearest-neighbor links. When applied to synthesizing arbitrary small rotations, distilling both T and square-root T states together achieves a 43 percent lower minimum logical error rate and 26 percent fewer resources than distilling T states alone. This is relevant for algorithms such as the quantum Fourier transform and phase estimation that rely on precise phase rotations.

Core claim

The central claim is that parity unfolding provides an efficient distillation method for gates at arbitrary levels of the Clifford hierarchy, enabling the fault-tolerant preparation of |Z_k> states with 2^{k+3} + O(2^{k/2}) qubits on planar nearest-neighbor biased-noise architectures. For algorithms needing native small rotations up to k=7, resource overheads decrease. Moreover, parity-unfolded distillation of T plus square-root T reduces the minimum achievable logical error rate by 43% and resource requirements by 26% compared to T-only unfolded distillation.

What carries the argument

parity unfolding: an efficient distillation procedure for magic states in the Clifford hierarchy that maintains noise bias on 2D nearest-neighbor layouts

If this is right

Algorithms like quantum Fourier transform and phase estimation see reduced overhead for rotations up to 1/32 precision.
Combined distillation of T and sqrt(T) states yields 43% better logical error rates than T-only methods.
Resource usage for arbitrary rotation synthesis drops by 26%.
The qubit scaling for preparing higher-order rotation states remains polynomial in 2^{k/2} on planar chips.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

The method opens the possibility of implementing phase estimation with lower physical qubit counts on current biased-noise devices if the bias is preserved.
Further optimizations might arise from integrating this with error-correcting codes tailored to bias.
Testing the approach on small k values could validate the scaling before larger implementations.

Load-bearing premise

The platform's noise bias is maintained during distillation and no significant unbiased errors are introduced by the circuit implementations.

What would settle it

Simulating or implementing the (T + sqrt(T)) parity-unfolded distillation circuit on a biased noise model and checking if the logical error rate is indeed 43% lower than the T-only version at the same resource level.

Figures

Figures reproduced from arXiv: 2604.15436 by Anette Messinger, Christophe Goeller, Christoph Fleckenstein, Josua Unger, Konstantin Tiurev, Matthias Traube, Nitica Sakharwade, Paul Schnabl, Wolfgang Lechner.

**Figure 2.** Figure 2: Distillation of logical state |Z˜m−2⟩ using QRM(1, m) code. (a) State distillation circuit consists of 2m − 1 qubits of the code QRM(1, m) and one target qubit. First, the target is entangled with one of the code qubits in a Bell pair. The code qubits are then encoded in the QRM(1, m) code. Subsequently, Z † m−2 gate are applied transversally to all qubits of the code, followed by X measurement of all of … view at source ↗

**Figure 5.** Figure 5: Examples of weight-4 stabilizers defined along the hor [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗

**Figure 4.** Figure 4: A full layout for distilling rotation Z4 using the unfolded code uRM(6). The layout is constructed step by step, as described throughout Sec. V. There are 26 bulk qubits (circles with labels), of which 26 − 1 are qubits of the QRM(1, 6) code (salmon) and one qubit of the target logical qubits (labelled 0). Each square plaquette corresponds to a weight-4 Z bulk stabilizer; there are (23 − 1)2 = 49 independe… view at source ↗

**Figure 6.** Figure 6: Construction of stabilizers S (w, t) from Eq. (10) and [PITH_FULL_IMAGE:figures/full_fig_p008_6.png] view at source ↗

**Figure 7.** Figure 7: Logical error rates for different values of bias η. (a) Logical error rate of a single-round distillation of state |Zk⟩ calculated using Eqs. (11) and (18). Curves for two different noise models are shown. Squares correspond to a constant noise model of Eq. (16), i.e., a situation where physical Zk rotations yield identical noise for all k. Since in this regime non-Clifford noise q(k) dominates over other… view at source ↗

**Figure 8.** Figure 8: Simulated logical error rates of the [PITH_FULL_IMAGE:figures/full_fig_p011_8.png] view at source ↗

**Figure 9.** Figure 9: Space-time overheads of applying a Zk rotation using parity-unfolded Ck gate set. Orange circles correspond to the exact and upper-bound expression Eq. (28). The horizontal line shows the cost of approximating Zk with gates from C2, i.e., the (Clifford + T) set, calculated according to Eq. (29). Here, we use η = 105 , ϵ = 10−3 and the rest or parameters are identical to those of [PITH_FULL_IMAGE:figures/f… view at source ↗

**Figure 10.** Figure 10: Average synthesis error ϵ as a function of total resource cost R for the unfolded C2 = (Clifford + T) and C3 = (Clifford + T + √ T) gate set. Each data point displays the average synthesis error for 100 Haar random unitaries. Dashed lines indicate fits to a log(1/ϵ)+b. Data points mark the median while error bars indicate the 68% confidence interval. With this, the total space-time cost of distilling the … view at source ↗

**Figure 12.** Figure 12: Total logical error rate [Eq. (38)] versus space-time cost [Eq. (39)] of approximating an arbitrary single-qubit unitary U using gate sets C2 and C3. The two curves shown for the set C3 correspond to the constant and scaled noise models, as defined by Eqs. (16) and (17), respectively. Noise parameters are the same as in [PITH_FULL_IMAGE:figures/full_fig_p014_12.png] view at source ↗

**Figure 13.** Figure 13: Boundary stabilizers with nearest-neighbour qubit connectivity. Shown are stabilizers along the horizontal boundaries of the [PITH_FULL_IMAGE:figures/full_fig_p021_13.png] view at source ↗

**Figure 14.** Figure 14: Same as in Fig [PITH_FULL_IMAGE:figures/full_fig_p021_14.png] view at source ↗

read the original abstract

We introduce the parity-unfolded architecture, a fault-tolerant quantum computing scheme that relies on direct preparation and teleportation of small-angle rotations $ Z^{1/2^{k}}$ rather than approximating them with the conventional (Clifford + $T$) gate set. The architecture is enabled by efficient distillation of gates from an arbitrary level of the Clifford hierarchy, which we refer to as parity unfolding. With it, a state $|Z_k\rangle = Z^{1/2^{k}}|{+}\rangle$ can be prepared fault-tolerantly using $2^{k+3} + O(2^{k/2})$ biased-noise qubits on a planar chip with nearest-neighbour connectivity. For algorithms requiring native $Z^{1/2^{k}}$ gates, such as the Quantum Fourier Transform and phase estimation, the proposed scheme allows to reduce resource overheads for up to $k=7$, i.e., up to $T^{1/32}$. Furthermore, when used for the synthesis of arbitrary small-angle rotations, parity-unfolded distillation of ($T$ + $\sqrt{T}$) reduces the minimum achievable logical error rate by 43% while cutting the resource requirements by 26%, when compared to unfolded distillation of only the $T$ gate.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

Parity unfolding is a concrete new distillation trick for higher-order Z rotations on biased-noise hardware, but the planar NN layout may not preserve the bias without extra cost.

read the letter

The core advance here is a distillation method they call parity unfolding that lets you prepare |Z_k> states directly instead of approximating them through repeated T gates. They pair this with teleportation so the whole thing runs on a 2D nearest-neighbor grid of biased-noise qubits, and they give an explicit count: 2^{k+3} plus an O(2^{k/2}) layout term. That scaling, plus the claim that mixing in sqrt(T) distillation cuts logical error by 43% and resources by 26% versus T-only, is the part that could actually move the needle for phase estimation and QFT on the right hardware.

Referee Report

2 major / 2 minor

Summary. The paper introduces a parity-unfolded distillation architecture for fault-tolerant quantum computing on noise-biased platforms. It enables direct preparation and teleportation of small-angle rotations Z^{1/2^k} from arbitrary levels of the Clifford hierarchy, rather than approximating them via Clifford+T. The central claims are that a state |Z_k⟩ can be prepared fault-tolerantly using 2^{k+3} + O(2^{k/2}) biased-noise qubits on a planar chip with nearest-neighbor connectivity, that this reduces overheads for algorithms such as QFT and phase estimation up to k=7, and that parity-unfolded distillation of (T + √T) yields a 43% reduction in minimum achievable logical error rate and 26% fewer resources compared to T-only distillation for arbitrary small-angle rotations.

Significance. If the noise-bias preservation holds under the stated planar NN layout, the work would offer a concrete route to lower-overhead synthesis of small-angle rotations and native implementation of QFT/phase estimation on biased-noise hardware. The explicit resource formulas (2^{k+3} + O(2^{k/2})) and numerical percentage gains constitute falsifiable, parameter-free predictions that strengthen the contribution relative to prior distillation literature.

major comments (2)

[§4.2, Figure 7] §4.2 and Figure 7: the error-propagation analysis for the parity-unfolded distillation circuit on the 2D NN grid does not provide an explicit gate schedule or SWAP/routing overhead calculation showing that introduced X/Y errors remain below the bias threshold; without this, the claimed 2^{k+3} + O(2^{k/2}) scaling and the 43%/26% gains cannot be verified as load-bearing.
[§3, Eq. (12)] §3, Eq. (12): the derivation of the 43% logical-error reduction for (T + √T) versus T-only distillation assumes the noise model remains strictly Z-biased after teleportation; a concrete bound on the X/Y leakage rate introduced by the planar layout is required to support this numerical claim.

minor comments (2)

[Abstract, §5.1] The abstract and §5.1 refer to 'up to k=7' without stating the precise resource crossover point versus standard Clifford+T synthesis; adding a table of overhead versus k would improve clarity.
[§2] Notation for the parity-unfolding operator is introduced in §2 but used without re-definition in later circuit diagrams; a short reminder equation would aid readability.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for their detailed and insightful comments on our manuscript. We have reviewed the major comments concerning the error-propagation analysis and the assumptions in the logical-error reduction calculation. We provide point-by-point responses below and will make the necessary revisions to enhance the clarity and verifiability of our results.

read point-by-point responses

Referee: [§4.2, Figure 7] §4.2 and Figure 7: the error-propagation analysis for the parity-unfolded distillation circuit on the 2D NN grid does not provide an explicit gate schedule or SWAP/routing overhead calculation showing that introduced X/Y errors remain below the bias threshold; without this, the claimed 2^{k+3} + O(2^{k/2}) scaling and the 43%/26% gains cannot be verified as load-bearing.

Authors: We agree that an explicit gate schedule and SWAP/routing overhead calculation would strengthen independent verification of the error propagation under the planar nearest-neighbor connectivity. The O(2^{k/2}) term in the resource count is intended to incorporate the routing overhead on the 2D grid, and the architecture is constructed to keep introduced X/Y errors suppressed relative to the bias threshold. In the revised manuscript we will add a supplementary section containing the detailed gate schedule together with the corresponding bound on X/Y error rates, thereby confirming that these errors remain below threshold and supporting both the scaling formula and the reported percentage gains. revision: yes
Referee: [§3, Eq. (12)] §3, Eq. (12): the derivation of the 43% logical-error reduction for (T + √T) versus T-only distillation assumes the noise model remains strictly Z-biased after teleportation; a concrete bound on the X/Y leakage rate introduced by the planar layout is required to support this numerical claim.

Authors: The 43% reduction quoted from Eq. (12) is obtained under the assumption that Z-bias is preserved through the teleportation step, which is a central property of the parity-unfolded protocol on biased-noise hardware. We acknowledge that a quantitative bound on any X/Y leakage induced by the planar routing would make this assumption fully rigorous. In the revision we will insert an explicit upper bound on the leakage rate, derived directly from the error-propagation analysis, and demonstrate that it is small enough to preserve the validity of the 43% figure. revision: yes

Circularity Check

0 steps flagged

No circularity: resource counts and error reductions are direct outputs of the new architecture

full rationale

The paper introduces the parity-unfolded distillation architecture as a novel scheme relying on direct preparation and teleportation of small-angle rotations rather than Clifford+T approximation. The quoted resource scaling 2^{k+3} + O(2^{k/2}) and the 43%/26% improvements for (T + √T) vs T-only are presented as consequences of this architecture's efficiency on biased-noise planar layouts. No equations, fitted parameters, or self-citations are shown reducing these quantities to prior inputs by construction; the derivation chain remains self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 0 invented entities

The central claims rest on standard quantum error correction assumptions plus platform-specific noise bias and connectivity constraints that are not quantified in the abstract; no free parameters or new entities are explicitly introduced in the provided text.

axioms (2)

domain assumption Noise is sufficiently biased that distillation circuits remain fault-tolerant at the stated overhead
Required for the 2^{k+3} scaling to hold on the target hardware
domain assumption Nearest-neighbor connectivity on a planar lattice is sufficient for the teleportation steps
Stated in the abstract as the physical setting

pith-pipeline@v0.9.0 · 5550 in / 1566 out tokens · 23488 ms · 2026-05-10T10:42:36.765509+00:00 · methodology

discussion (0)

Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

Local distillation from Reed Muller codes unfolding
quant-ph 2026-05 unverdicted novelty 6.0

Local 2D and 3D Reed-Muller distillation factories achieve output infidelities down to 8.256e-9 for CCZ states and 1.1811e-17 for T states from 10^{-3} input infidelity.

Reference graph

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