pith. sign in

arxiv: 2604.21625 · v2 · pith:ON6S2PRUnew · submitted 2026-04-23 · ❄️ cond-mat.mes-hall · hep-ex

DC Cryogenic Modeling of Open-Source SkyWater 130 nm MOSFETs at 77 K Using BSIM4

F.Beall , A.Rimal , O.Seidel , Y.Mei , A.D.McDonald , I. Parmaksiz , V.A.Chirayath , J.Asaadi
show 2 more authors
D.Braga J.B.R.Battat
This is my paper

Pith reviewed 2026-07-04 22:40 UTC · model glm-5.2

classification ❄️ cond-mat.mes-hall hep-ex
keywords cryogenicapplicationscmosliquidmodelmodelingopen-sourcesky130
0
0 comments X

The pith

First open-source 77K transistor models for SkyWater 130nm

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper presents the first systematic DC characterization and BSIM4-based isothermal modeling of SkyWater 130nm (SKY130) MOSFETs at 77K, the operating temperature of liquid argon detectors used in high-energy physics. The authors measured DC current-voltage curves for 22 transistors (8 nMOS, 14 pMOS) across a range of geometries at both room temperature and 77K, then built eighteen distinct SPICE-compatible cryogenic models by adjusting just seven BSIM4 parameters — threshold voltage (VTH0), low-field mobility (U0), source/drain resistance (RDSW), subthreshold swing factor (NFACTOR), saturation velocity (VSAT), drain-induced barrier lowering coefficient (ETA0), and linear-to-saturation smoothing (DELTA) — through multiplicative scaling factors applied to the existing room-temperature foundry values. This scaling-factor approach preserves the original PDK's structure for process corners and mismatch while shifting the model to cryogenic behavior. The resulting models achieve an average relative RMS error of approximately 20% across all measured devices, comparable to the room-temperature data-model agreement, with no systematic dependence of error on drain bias. The models are publicly available and NGSpice-compatible, establishing SKY130 as a practical open-source node for 77K cryogenic circuit design.

Core claim

The central claim is that a small set of seven physics-motivated BSIM4 parameters, adjusted via multiplicative scaling factors on top of the existing room-temperature SKY130 PDK, is sufficient to produce SPICE-compatible isothermal transistor models at 77K with roughly 20% relative RMS error and no drain-voltage-dependent systematic bias. The method preserves the original PDK's process variation and mismatch structure because it scales rather than replaces the foundry parameters. Eighteen per-bin models were generated covering both nMOS and pMOS across a range of channel lengths and widths, and the error metrics at 77K are comparable to — and in some cases better than — the room-temperature

What carries the argument

The load-bearing mechanism is the multiplicative scaling-factor approach: instead of re-extracting all BSIM4 parameters from scratch at 77K, the authors insert nominal scaling parameters (defaulting to 1.0) that multiply the original foundry-verified BSIM4 values. This preserves the PDK's internal correlations, mismatch models, and process corner definitions while shifting the seven most temperature-sensitive parameters to their 77K values. The extraction is performed per geometry bin using the Synopsys Mystic optimizer against measured I-V curves, with a staged fitting strategy that extracts parameter groups against specific regions of the transfer and output characteristics (e.g., VTH0/U0/

If this is right

  • Circuit designers targeting liquid argon detector readout (77-89K) can now simulate SKY130 circuits at operating temperature using open-source, SPICE-compatible models, removing a key barrier to adopting this node for cryogenic HEP instrumentation.
  • The scaling-factor methodology could be applied to other open-source PDKs (e.g., GlobalFoundries 180nm, IHP 130nm BiCMOS) to rapidly produce cryogenic models without full re-extraction, accelerating cryogenic PDK development across nodes.
  • The 77K models provide a baseline intermediate-temperature anchor between existing 300K and 4K SKY130 characterizations, potentially enabling interpolation or extrapolation to other cryogenic temperatures relevant to quantum computing or space applications.
  • The per-bin extraction approach means that untested geometries falling outside the eighteen modeled bins lack cryogenic coverage, motivating expansion of the geometry space in future work.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If the seven-parameter scaling approach generalizes to other CMOS nodes, it suggests that cryogenic compact modeling may not require full re-extraction pipelines but can instead leverage the physics-guided parameter selection strategy demonstrated here, significantly reducing the effort barrier for cryogenic PDK creation.
  • The observation that 77K model accuracy is comparable to room-temperature accuracy implies that the dominant cryogenic effects at this temperature are well-captured by threshold voltage shift, mobility enhancement, series resistance change, subthreshold slope modification, and velocity saturation adjustment — suggesting that more exotic cryogenic physics (e.g., interface trap redistribution, incom
  • The lack of drain-voltage-dependent systematic error suggests the model captures DIBL and saturation behavior adequately at 77K, but the authors note the models are DC-only; AC, noise, and capacitance behavior at 77K remain uncharacterized, and analog designers relying on transconductance accuracy or flicker noise should treat the DC-level validation as necessary but not sufficient.
  • The large scaling factors observed for some parameters (e.g., NFACTOR multiplied by factors of 30-50 in some bins, VSAT changing by orders of magnitude in pMOS) may indicate that the scaling-factor approach is pushing the BSIM4 model into regimes where the original parameter correlations are strained, potentially limiting extrapolation reliability for geometries or bias conditions not directly mea

Load-bearing premise

The modeling approach assumes that adjusting only seven BSIM4 parameters via multiplicative scaling is sufficient to capture all relevant cryogenic physics at 77K, while leaving all other parameters at their room-temperature foundry values. If significant low-temperature effects — such as incomplete dopant ionization affecting capacitance, interface trap density changes, or temperature-dependent velocity overshoot — are not adequately represented by these seven parameters,

What would settle it

A transistor geometry or bias regime not included in the eighteen modeled bins, when measured at 77K, would show DC I-V behavior that the scaled BSIM4 model cannot reproduce within the ~20% relative RMS error achieved on the characterized devices.

read the original abstract

Cryogenic applications in high-energy physics (HEP) demand reliable, low-power CMOS electronics capable of operating at liquid nitrogen temperatures (77 K). The open-source SkyWater 130 nm (SKY130) CMOS process has previously been shown to operate at temperatures as low as 4 K making it a promising candidate for HEP applications. In this work, we characterize and model SKY130 low-threshold voltage transistors at 77 K, which is a temperature commonly used in modeling applications for liquid argon detectors. DC characteristic measurements were performed at both room temperature and liquid nitrogen temperature. We created a cryogenic modeling approach to produce a SPICE-compatible, isothermal BSIM4-based model for select transistor sizes at 77 K. The resulting model agrees with data at 77 K with an average error on the order of 20% (relative RMS) and shows no dependence on drain voltage. Due to the open-source nature of SKY130, we have made our models publicly available on Github. We hope this work will continue the trend for democratizing circuit design at cryogenic temperatures in high-energy physics by enabling open access to accurate CMOS device models at 77 K.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 7 minor

Summary. This manuscript presents the first systematic DC characterization and BSIM4-based isothermal modeling of SkyWater 130 nm (SKY130) MOSFETs at 77 K, targeting cryogenic electronics for liquid argon time projection chambers. Twenty-two transistors (8 nMOS, 14 pMOS) were measured at 300 K and 77 K, yielding eighteen binned models. Seven BSIM4 parameters (VTH0, U0, RDSW, NFACTOR, VSAT, ETA0, DELTA) are extracted via multiplicative scaling factors using the Synopsys Mystic optimizer. The authors report an average relative RMS error (RRMS) of approximately 20% and note no drain-voltage dependence of the error. The models and raw data are publicly released on GitHub.

Significance. The work addresses a genuine gap: SKY130 is the only fully open-source CMOS PDK, and no 77 K model previously existed for this node. The decision to release both the models and the underlying measurement data on GitHub is a clear strength that enables community verification and extension. The multiplicative-scaling extraction strategy that preserves the foundry PDK's process-corner and mismatch structure is a sensible design choice for a cryogenic PDK. The paper is well-organized and the physics background (Section 2) is adequate for the target audience.

major comments (1)
  1. Table 4, pMOS bins: Several extracted VSAT values are physically implausible. For example, the L=8µm W=1.6µm pMOS bin shows VSAT changing from 1.03×10^5 (300K) to 1.03×10^9 (77K) — a factor of ~10,000 increase. Saturation velocity in silicon is ~10^7 cm/s at 300K and may increase by at most a factor of ~2 at 77K; values of 10^8–10^9 cm/s have no physical basis. Similarly, RDSW drops from 485 to 5.40×10^-3 for the L=8µm W=1.6µm pMOS bin (a ~90,000× decrease), and NFACTOR scaling factors reach 50×. These extreme values suggest the optimizer is using VSAT and RDSW as unconstrained mathematical fitting knobs to compensate for missing cryogenic physics (e.g., LDD freeze-out, interface trap effects). The manuscript does not discuss these physically implausible values or impose bounds that would keep parameters within credible ranges. This is load-bearing for the central claim of practicality:
minor comments (7)
  1. Section 5.1: The convergence criterion is described as 'three iterations or RMSD below 10 µA.' Three iterations is a very small number for a seven-parameter optimization; please justify that this is sufficient for convergence and report whether the RMSD threshold or the iteration limit was the binding constraint for each bin.
  2. Table 4 caption: The note about VTH0 and NFACTOR being 'listed in a functional form' with symbols * and # is unclear. Readers cannot verify the actual extracted values without consulting the BSIM4 manual. Please state the functional form explicitly or provide the effective numerical values.
  3. Section 5.4, Eq. (5.1): The RRMS denominator uses the mean of |I_data|. This means the metric is dominated by high-current regions; errors in the subthreshold regime are systematically downweighted. Please acknowledge this limitation when discussing the subthreshold fit quality.
  4. Figure 5: The bar chart shows RRMS per transistor but does not distinguish nMOS from pMOS visually. Given the bimodal error distribution, a color or pattern distinction would help readers assess the two populations separately.
  5. Section 3: The chamber pressure is stated as 'maintained at maintained at 2mTorr' — duplicate text. Also, the RTD type and calibration are not specified; please add for reproducibility.
  6. Tables 1–2: The binning logic ('if that model bin has already been assigned to a different transistor, the neighboring bin is chosen') is ambiguous. Please clarify whether the neighboring bin's parameters were then extracted from the device in question or from a different device.
  7. Abstract and Section 6: The claim of 'no dependence on drain voltage' is based on visual inspection of error spread (Section 5.4). Please state this more precisely — is it a qualitative observation or was a statistical test applied?

Simulated Author's Rebuttal

1 responses · 0 unresolved

The referee correctly identifies that several extracted BSIM4 parameter values in Table 4 are physically implausible, particularly VSAT values reaching 10^8-10^9 cm/s for pMOS bins and extreme RDSW and NFACTOR scaling factors. We acknowledge this is a genuine and important concern. The referee's diagnosis—that the optimizer is using these parameters as unconstrained mathematical fitting knobs to compensate for missing cryogenic physics—is substantially correct. We will revise the manuscript to (1) impose physically motivated bounds on VSAT and RDSW during extraction, (2) re-extract affected bins with constrained optimization, and (3) add an explicit discussion of parameter plausibility and the limitations of using BSIM4 without cryogenic-specific physics extensions (e.g., LDD freeze-out, interface trap modeling). We disagree only with the implication that the entire modeling approach is invalidated; the multiplicative-scaling strategy itself is sound, but the lack of bounds on certain parameters was an oversight that we will correct.

read point-by-point responses

  1. Referee: Table 4, pMOS bins: Several extracted VSAT values are physically implausible. For example, the L=8µm W=1.6µm pMOS bin shows VSAT changing from 1.03×10^5 (300K) to 1.03×10^9 (77K) — a factor of ~10,000 increase. Saturation velocity in silicon is ~10^7 cm/s at 300K and may increase by at most a factor of ~2 at 77K; values of 10^8–10^9 cm/s have no physical basis. Similarly, RDSW drops from 485 to 5.40×10^-3 for the L=8µm W=1.6µm pMOS bin (a ~90,000× decrease), and NFACTOR scaling factors reach 50×. These extreme values suggest the optimizer is using VSAT and RDSW as unconstrained mathematical fitting knobs to compensate for missing cryogenic physics (e.g., LDD freeze-out, interface trap effects). The manuscript does not discuss these physically implausible values or impose bounds that would keep parameters within credible ranges.

    Authors: The referee is correct on all counts. The VSAT values of 10^8–10^9 cm/s for several pMOS bins are physically implausible: the saturation velocity in silicon is approximately 10^7 cm/s at 300K and can increase by at most a factor of ~2 at 77K. Similarly, the RDSW decrease of ~90,000× and NFACTOR scaling factors of 50× have no physical basis. The referee's diagnosis is also correct: the Synopsys Mystic optimizer was run without sufficiently stringent physical bounds on these parameters, and it exploited VSAT and RDSW as unconstrained mathematical fitting knobs to compensate for cryogenic physics not captured by the standard BSIM4 framework—most notably LDD freeze-out and interface trap effects, both of which we discuss in Section 2 but do not explicitly model in the extraction. We will address this in the revised manuscript through three concrete changes: (1) We will impose physically motivated bounds on VSAT (e.g., limiting the 77K value to at most 3× the 300K value) and RDSW (e.g., constraining the scaling factor to a physically credible range consistent with LDD freeze-out literature) during the Mystic optimization. (2) We will re-extract all affected pMOS bins with these constraints and report updated parameter values and RRMS errors. We expect some degradation in fit quality for the most affected bins, which we will report transparently. (3) We will add a new subsection in Section 5 discussing parameter plausibility, the limitations of using standard BSIM4 without cryogenic physics extensions, and the specific mechanisms (LDD freeze-out, interface trap capacitance) that the unbounded optimizer was implicitly compensating for. We note that the nMOS bins, which generally show more physically reasonable parameter values, are less affected. The multiplicative-scaling-ex- revision: no

Circularity Check

0 steps flagged

No significant circularity: the paper fits BSIM4 parameters to measured 77K I-V data and reports accuracy on the same data, which is standard compact-model extraction practice, not a hidden circularity.

full rationale

The paper extracts seven BSIM4 parameters (VTH0, U0, RDSW, NFACTOR, VSAT, ETA0, DELTA) per geometry bin by fitting to measured 77K I-V curves using the Mystic optimizer, then reports RRMS error against those same curves. This is standard compact-model extraction: parameters are fitted to data and goodness-of-fit is reported on the fitted data. The paper does not claim to predict held-out or out-of-sample bias points; it claims the models 'agree with data at 77K' and are 'comparable, and in some cases, better than, the room temperature data-model agreement.' The room-temperature PDK serves as an external starting point (foundry-verified, unchanged parameters), and the 77K measurements are independently acquired. The absence of cross-validation is a generalizability limitation (correctly flagged by the reader and acknowledged in Section 6: 'has not yet experimentally validated mismatch or process corner variations'), but it is not circularity—the fit is not disguised as a prediction of different data. The physics discussion in Section 2 cites external literature (Beckers, Hafez, Arora, etc.) for expected cryogenic trends, and these citations are not load-bearing for the extraction itself. No self-citation chain is used to forbid alternatives or smuggle in an ansatz. The physically implausible pMOS parameter values noted by the skeptic are a correctness/overfitting concern, not a circularity concern. The derivation is self-contained against external benchmarks (measured I-V data), and the finding is no significant circularity.

Axiom & Free-Parameter Ledger

7 free parameters · 4 axioms · 0 invented entities

The paper introduces no new physical entities, particles, or forces. All seven free parameters are standard BSIM4 model parameters fitted to measured data. The multiplicative scaling approach is a modeling choice, not a new entity. The axioms are domain assumptions standard in compact model extraction, though the sufficiency of seven parameters and the isothermal assumption are not independently verified.

free parameters (7)
  • VTH0 scaling factor = 1.06–4.85 (varies by bin)
    Multiplicative scaling of threshold voltage parameter, extracted per bin against low-VDS transfer curves at 77K.
  • U0 scaling factor = varies by bin, e.g., 7.40e-2 to 0.29 for nMOS
    Multiplicative scaling of low-field mobility, extracted per bin against low-VDS transfer curves at 77K.
  • RDSW scaling factor = varies by bin, e.g., 100 to 288 for nMOS
    Multiplicative scaling of LDD source/drain resistance, extracted per bin against low-VDS transfer curves at 77K.
  • NFACTOR scaling factor = 2.41–50 (varies by bin)
    Multiplicative scaling of subthreshold swing factor, extracted per bin against low-VDS transfer curves at 77K.
  • VSAT scaling factor = varies widely by bin
    Multiplicative scaling of saturation velocity, extracted per bin against output curves and high-VDS transfer curves at 77K.
  • ETA0 scaling factor = varies by bin, only for short-channel devices
    Multiplicative scaling of DIBL coefficient, extracted for select short devices against high-VDS transfer curves.
  • DELTA scaling factor = varies by bin, only when visually poor fit
    Multiplicative scaling of linear-to-saturation smoothing, extracted against output curves when visual fit is poor.
axioms (4)
  • domain assumption BSIM4 model framework accurately captures cryogenic MOSFET behavior at 77K with only seven parameters adjusted.
    Section 2 and 5.2: The paper selects seven BSIM4 parameters to adjust while leaving all others at room-temperature foundry values. This assumes the remaining ~100+ BSIM4 parameters do not need cryogenic adjustment.
  • domain assumption DC I-V characteristics are sufficient for cryogenic modeling; C-V characteristics do not require separate cryogenic extraction.
    Section 5.1: 'only DC characteristics are used, since previous C-V studies suggest the dominant low-temperature effect on intrinsic gate-capacitance is a shift in bias axis associated with VTH.'
  • domain assumption Multiplicative scaling of foundry BSIM4 parameters preserves the physical validity of process-corner and mismatch variations at 77K.
    Section 5.1: 'This strategy preserves the underlying PDK dynamics of the original BSIM4 parameters, such as mismatch and process corner variations.' This is assumed but not verified at 77K.
  • domain assumption The isothermal assumption (no self-heating) is valid at 77K for the measured bias conditions.
    The model is described as 'isothermal' throughout. At 77K, thermal conductivity of silicon is high and self-heating effects may differ from room temperature, but this assumption is not explicitly justified.

pith-pipeline@v1.1.0-glm · 19555 in / 3411 out tokens · 172555 ms · 2026-07-04T22:40:38.551042+00:00 · methodology

Review history (2 revisions) →

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Reference graph

Works this paper leans on

41 extracted references · 41 canonical work pages

  1. [1]

    Specifically, Equation (2.32) defines the channel-length-dependent DIBL coefficient�DIBL 𝑡 ℎ , and Equation (2.33) gives the corresponding threshold-voltage shift as �� �DIBL� 𝑡 ℎ ��� DIBL 𝑡 ℎ �ETA0�ETAB�� 𝐵𝑆�� 𝐷𝑆 �(2.8) Thus, within the BSIM4 framework,ETA0is the primary DIBL coefficient in the subthreshold region,whileETABisthebody-biascoefficientforthe...

    work page 2023

  2. [2]

    Open-source-PDKs

    Google, “Open-source-PDKs.”https://github.com/google/open-source-pdks

    work page

  3. [3]

    Open source PDK in 130nm BiCMOS, developed for analog/digital, mixed signal and RF ASIC design

    Leibniz Institute for High Performance Microelectronics, “Open source PDK in 130nm BiCMOS, developed for analog/digital, mixed signal and RF ASIC design.” https://www.ihp-microelectronics.com/services/ research-and-prototyping-service/fast-design-enablement/open-source-pdk

    work page

  4. [4]

    Akturk, A

    A. Akturk, A. Tripathi and M. Saligane,Cryogenic modeling for open-source process design kit technology, in2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), pp. 58–65, 2023, DOI

    work page 2023

  5. [5]

    IHP RFIC Interoperable Cryogenic PDK

    A. Datsuk, “IHP RFIC Interoperable Cryogenic PDK.” https://indico.cern.ch/event/1179742/contributions/5008661/attachments/ 2503235/4300512/MONOLITH_Workshop_AntonDatsuk.pdf, 2022

    work page arXiv 2022

  6. [6]

    P. Fath, M. Moser, G. Zachl and H. Pretl,Open-source design of integrated circuits,e+i Elektrotechnik und Informationstechnik���(2024) 76

    work page 2024

  7. [7]

    Raheem, P.R.A

    M.A. Raheem, P.R.A. Khan, M.M. Hyder and M. Zeeshan,Design of a 3-bit full custom Flash ADC using skywater 130nm PDK for real time control systems, in2025 Devices for Integrated Circuit (DevIC), pp. 375–379, 2025, DOI

    work page 2025

  8. [8]

    Design of a linear transconductance OTA using the Open Sky130 process design kit

    C.V. Souza, E.P. Ribeiro and E.C. Teixeira, “Design of a linear transconductance OTA using the Open Sky130 process design kit.”https://zenodo.org/records/10646550

    work page arXiv

  9. [9]

    Acerbi, P

    F. Acerbi, P. Adhikari, P. Agnes, I. Ahmad, S. Albergo, I.F.M. Albuquerque et al.,Darkside-20k sensitivity to light dark matter particles,Communications Physics�(2024) 422

    work page 2024

  10. [10]

    Asaadi, D.A

    J. Asaadi, D.A. Dwyer and B. Russell,Novel liquid argon time-projection chamber readouts,Annual Review of Nuclear and Particle Science��(2024) 529. [10]MicroBooNEcollaboration,Design and Construction of the MicroBooNE Detector,JINST�� (2017) P02017 [1612.05824]

    work page arXiv 2024

  11. [11]

    Abed Abud, B

    A. Abed Abud, B. Abi, R. Acciarri, M.A. Acero, M.R. Adames, G. Adamov et al.,Performance of a modular ton-scale pixel-readout liquid argon time projection chamber,Instruments�(2024)

    work page 2024

  12. [12]

    Berns, H

    H.-G. Berns, H. Chen, A. D’Andragora, J. Fried, D. Gastler, S. Gao et al.,Front-end readout electronics system of ProtoDUNE-SP LAr TPC,Radiation Detection Technology and Methods� (2019) 42

    work page 2019

  13. [13]

    Gao and on behalf of the DUNE Collaboration,Cold readout electronics for liquid argon TPCs in the DUNE experiment,Journal of Physics: Conference Series����(2022) 012075

    S. Gao and on behalf of the DUNE Collaboration,Cold readout electronics for liquid argon TPCs in the DUNE experiment,Journal of Physics: Conference Series����(2022) 012075

    work page 2022

  14. [14]

    Beckers, F

    A. Beckers, F. Jazaeri, A. Ruffino, C. Bruschini, A. Baschirotto and C. Enz,Cryogenic characterization of 28 nm bulk cmos technology for quantum computing, in2017 47th European Solid-State Device Research Conference (ESSDERC), pp. 62–65, 2017, DOI

    work page 2017

  15. [15]

    Zhao and X

    H. Zhao and X. Liu,Modeling of a standard 0.35�m cmos technology operating from 77k to 300k, Cryogenics��(2014) 49

    work page 2014

  16. [16]

    C. Luo, Z. Li, T.-T. Lu, J. Xu and G.-P. Guo,Mosfet characterization and modeling at cryogenic temperatures,Cryogenics��(2019) 12

    work page 2019

  17. [17]

    De Geronimo, A

    G. De Geronimo, A. D’Andragora, S. Li, N. Nambiar, S. Rescia, E. Vernon et al.,Front-end asic for a liquid argon tpc,IEEE Transactions on Nuclear Science��(2011) 1376. – 21 –

    work page 2011

  18. [18]

    J.Hoff, R.Arora,J.Cressler, G.Deptuch,P.Gui, N.Lourencoetal.,Lifetimestudiesof130nmnMOS transistors intended for long-duration, cryogenic high-energy physics experiments,IEEE Transactions on Nuclear Science��(2012)

    work page 2012

  19. [19]

    SkyWater Open Source PDK

    Google and SkyWater Technology Foundry, “SkyWater Open Source PDK.” https://github.com/google/skywater-pdk

    work page

  20. [20]

    BSIM group, Berkeley, CA,BSIM4 4.8.3 MOSFET model: User’s manual, 2025

    work page 2025

  21. [21]

    Beckers, F

    A. Beckers, F. Jazaeri and C. Enz,Cryogenic MOS transistor model,IEEE Transactions on Electron Devices��(2018) 3617

    work page 2018

  22. [22]

    Beckers, F

    A. Beckers, F. Jazaeri, A. Grill, S. Narasimhamoorthy, B. Parvais and C. Enz,Physical model of low-temperature to cryogenic threshold voltage in MOSFETs,IEEE Journal of the Electron Devices Society�(2020) 780

    work page 2020

  23. [23]

    N.C. Dao, A. El Kass, M.R. Azghadi, C.T. Jin, J. Scott and P.H. Leong,An enhanced MOSFET threshold voltage model for the 6–300 k temperature range,Microelectronics Reliability��(2017) 36

    work page 2017

  24. [24]

    Arora and G

    N. Arora and G. Gildenblat,A semi-empirical model of the mosfet inversion layer mobility for low-temperature operation,IEEE Transactions on Electron Devices��(1987) 89

    work page 1987

  25. [25]

    Cheng and J

    B. Cheng and J. Woo,A temperature-dependent mosfet inversion layer carrier mobility model for device and circuit simulation,IEEE Transactions on Electron Devices��(1997) 343

    work page 1997

  26. [26]

    Beckers, F

    A. Beckers, F. Jazaeri and C. Enz,Theoretical limit of low temperature subthreshold swing in field-effect transistors,IEEE Electron Device Letters��(2020) 276

    work page 2020

  27. [27]

    Kamgar,Subthreshold behavior of silicon MOSFETs at 4.2K,Solid-State Electronics��(1982) 537

    A. Kamgar,Subthreshold behavior of silicon MOSFETs at 4.2K,Solid-State Electronics��(1982) 537

    work page 1982

  28. [28]

    Beckers, F

    A. Beckers, F. Jazaeri and C. Enz,Characterization and modeling of 28-nm bulk CMOS technology down to 4.2K,IEEE Journal of the Electron Devices Society�(2018) 1007

    work page 2018

  29. [29]

    Nguyen-Duc, S

    C. Nguyen-Duc, S. Cristoloveanu and G. Ghibaudo,Low-temperature mobility behaviour in submicron MOSFETs and related determination of channel length and series resistance,Solid-State Electronics��(1986) 1271

    work page 1986

  30. [30]

    Andhare, R

    P. Andhare, R. Nahar, N. Devashrayee, S. Chandra and W. Khokle,Development and performance characterization of the lightly doped drain MOS transistor,Microelectronics Reliability��(1990) 681

    work page 1990

  31. [31]

    Hafez, G

    I. Hafez, G. Ghibaudo, F. Balestra and M. Haond,Impact of LDD structures on the operation of silicon MOSFETs at low temperature,Solid-State Electronics��(1995) 419

    work page 1995

  32. [32]

    Efabless open MPW program

    “Efabless open MPW program.”https://efabless.com/open_shuttle_program

    work page

  33. [33]

    Balestra and G

    F. Balestra and G. Ghibaudo,Physics and performance of nanoscale semiconductor devices at cryogenic temperatures,Semiconductor Science and Technology��(2017)

    work page 2017

  34. [34]

    Skywater 130nm 77K cryogenic models

    F. Beall and A. Rimal, “Skywater 130nm 77K cryogenic models.”https://github.com/ UTA-Advanced-Detector-Technologies/Skywater-130nm-77K-Cryogenic-Models

    work page

  35. [35]

    fossi-foundation, “ciel.”https://github.com/fossi-foundation/ciel

    work page

  36. [36]

    open_PDKs

    R.T. Edwards, “open_PDKs.”https://github.com/rtimothyedwards/open_pdks, 2026

    work page 2026

  37. [37]

    Gatti and F

    A. Gatti and F. Tavernier,Cryogenic small dimension effects and design-oriented scalable compact modelingofa65-nmCMOStechnology,IEEEJournaloftheElectronDevicesSociety��(2024)369. – 22 –

    work page 2024

  38. [38]

    Incandela, L

    R.M. Incandela, L. Song, H. Homulle, E. Charbon, A. Vladimirescu and F. Sebastiano, Characterization and compact modeling of nanometer CMOS transistors at deep-cryogenic temperatures,IEEE Journal of the Electron Devices Society�(2018) 996

    work page 2018

  39. [39]

    T. Lu, Y. Zhang, Y. Zhang, J. Xu, G. Guo and C. Luo,Cryogenic modeling of MOSFET device based on BSIM and EKV models,arXiv(2021)

    work page 2021

  40. [40]

    Synopsys, “Mystic.” https://www.synopsys.com/manufacturing/tcad.html#tcad-to-spice, 2023

    work page 2023

  41. [41]

    PrimseSim HSPICE

    Synopsys, “PrimseSim HSPICE.”https://www.synopsys.com/ implementation-and-signoff/ams-simulation/primesim-hspice.html. – 23 –

    work page