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arxiv: 2604.22086 · v1 · submitted 2026-04-23 · 🪐 quant-ph · cond-mat.mtrl-sci

Recognition: unknown

Tantalum Damascene Coplanar Waveguide Resonators Fabricated Using 300 mm Scale Processes

Ekta Bhatia , Yingge Du , Krishna P Koirala , Chung Kow , Mingzhao Liu , Juan Macy , Tharanga R. Nanayakkara , Francisco Ponce
show 7 more authors
Satyavolu S. Papa Rao Drew J. Rebar Peter V. Sushko Brent A VanDevender Chongmin Wang Marvin G. Warner Zhihao Xiao
Authors on Pith no claims yet

Pith reviewed 2026-05-09 21:14 UTC · model grok-4.3

classification 🪐 quant-ph cond-mat.mtrl-sci
keywords superconducting resonatorsdamascene processtantalumsurface oxide lossescoplanar waveguidequantum devices300 mm fabrication
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The pith

Damascene fabrication replaces sidewall native oxides in tantalum resonators with metal-substrate interfaces to reduce losses.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper tests whether the damascene process can lower losses in superconducting resonators by swapping native sidewall oxides for cleaner metal-substrate contacts. Surface oxides on device sidewalls add dissipation that limits performance in quantum devices. The authors fabricate tantalum coplanar waveguide resonators on 300 mm wafers and bury an oxide layer during processing to mimic sidewall oxidation effects. They record a modest performance gain in the damascene devices relative to controls. The result points to a lower surface participation ratio as the source of the improvement.

Core claim

Tantalum damascene coplanar waveguide resonators made with 300 mm scale processes that include a buried oxide layer show modest improvement over reference devices. The authors attribute this to replacement of native sidewall oxide with a metal-substrate interface, which lowers the surface participation ratio.

What carries the argument

The damascene process that buries an oxide layer during fabrication to create a metal-substrate interface in place of native sidewall oxide.

Load-bearing premise

Burying an oxide layer during fabrication accurately simulates the loss contribution of native sidewall oxidation in actual devices.

What would settle it

Direct comparison of measured loss rates or quality factors in resonators that have genuine native sidewall oxides versus the buried-oxide simulation under otherwise identical conditions.

Figures

Figures reproduced from arXiv: 2604.22086 by Brent A VanDevender, Chongmin Wang, Chung Kow, Drew J. Rebar, Ekta Bhatia, Francisco Ponce, Juan Macy, Krishna P Koirala, Marvin G. Warner, Mingzhao Liu, Peter V. Sushko, Satyavolu S. Papa Rao, Tharanga R. Nanayakkara, Yingge Du, Zhihao Xiao.

Figure 1
Figure 1. Figure 1: FIG. 1. Damascene process flow for fabricating tantalum-based su [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. Scanning electron microscope (SEM) images depicting an [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. Electric field distribution profiles of the quarter-wave reso [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. (A) STEM image of a Device A type showing clearly defined [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8. (A) STEM image of a Device E type showing clearly defined [PITH_FULL_IMAGE:figures/full_fig_p004_8.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6. (A) STEM image of a Device C type showing clearly defined [PITH_FULL_IMAGE:figures/full_fig_p004_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7. (A) STEM image of a Device D type showing clearly defined [PITH_FULL_IMAGE:figures/full_fig_p004_7.png] view at source ↗
Figure 10
Figure 10. Figure 10: FIG. 10. (Top) Raw data from VNA for both narrow and wide band [PITH_FULL_IMAGE:figures/full_fig_p005_10.png] view at source ↗
Figure 9
Figure 9. Figure 9: FIG. 9. Full scan of (top) magnitude and (bottom) phase of [PITH_FULL_IMAGE:figures/full_fig_p005_9.png] view at source ↗
Figure 12
Figure 12. Figure 12: FIG. 12. Internal quality factor as a function of Temperature over [PITH_FULL_IMAGE:figures/full_fig_p006_12.png] view at source ↗
Figure 11
Figure 11. Figure 11: FIG. 11 [PITH_FULL_IMAGE:figures/full_fig_p006_11.png] view at source ↗
Figure 13
Figure 13. Figure 13: FIG. 13. Quality factor for the seven devices under test at 25 mK and [PITH_FULL_IMAGE:figures/full_fig_p007_13.png] view at source ↗
read the original abstract

Surface oxides contribute to losses in superconducting transmon devices resulting in degraded performance. We explore the use of the damascene process to replace the sidewall native oxide of a device with a metal/substrate interface. We simulate sidewall oxidation by burying an oxide layer during fabrication. We observe a modest improvement between the two types of devices, which is suggestive of a reduction in the surface participation ratio.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 0 minor

Summary. The manuscript investigates tantalum damascene coplanar waveguide resonators fabricated on 300 mm wafers as a means to mitigate losses from surface oxides in superconducting quantum devices. The authors replace sidewall native oxide with a metal/substrate interface using the damascene process and simulate sidewall oxidation by burying an oxide layer during fabrication. They report a modest improvement in the damascene devices relative to standard ones, which they interpret as suggestive of a reduced surface participation ratio.

Significance. If the central observation holds with supporting quantitative data, the work could demonstrate a scalable, semiconductor-compatible route to lowering dielectric losses in resonators by altering surface interfaces. This would be relevant to quantum hardware fabrication, though the current lack of metrics and validation of the simulation limits immediate impact.

major comments (2)
  1. [Abstract] Abstract: the claim of observing 'a modest improvement' is presented without any quantitative metrics (e.g., Q-factors, loss tangents, or participation ratios), error bars, statistical analysis, or specific process parameters, leaving the data-to-claim link undemonstrated and preventing assessment of whether the improvement is statistically meaningful or load-bearing for the interpretation.
  2. [Abstract] Abstract: the suggestion that the improvement indicates a reduction in surface participation ratio rests on the buried-oxide layer accurately proxying native sidewall oxidation losses. Native oxides form conformally at ~1-3 nm with specific stoichiometry and interface states on etched sidewalls, while a buried layer is typically thicker, planarized, and located at a different metal-substrate interface; these differences in thickness, dielectric constant, electric-field participation, and TLS density could produce the shift for unrelated reasons, requiring explicit justification or additional controls.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the careful review and constructive feedback on our manuscript. We address each major comment below and will revise the manuscript to improve clarity and support for our claims.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the claim of observing 'a modest improvement' is presented without any quantitative metrics (e.g., Q-factors, loss tangents, or participation ratios), error bars, statistical analysis, or specific process parameters, leaving the data-to-claim link undemonstrated and preventing assessment of whether the improvement is statistically meaningful or load-bearing for the interpretation.

    Authors: We agree that the abstract would be strengthened by including key quantitative results. The full manuscript contains measured Q-factors, loss tangents, and process details in the results and methods sections, along with error bars and statistical context from multiple devices. In the revised version, we will update the abstract to explicitly state representative Q-factor values for both device types, the observed improvement magnitude, and a brief reference to the supporting analysis. revision: yes

  2. Referee: [Abstract] Abstract: the suggestion that the improvement indicates a reduction in surface participation ratio rests on the buried-oxide layer accurately proxying native sidewall oxidation losses. Native oxides form conformally at ~1-3 nm with specific stoichiometry and interface states on etched sidewalls, while a buried layer is typically thicker, planarized, and located at a different metal-substrate interface; these differences in thickness, dielectric constant, electric-field participation, and TLS density could produce the shift for unrelated reasons, requiring explicit justification or additional controls.

    Authors: We acknowledge the physical differences between a buried oxide layer and native sidewall oxides, including thickness, conformality, and interface characteristics. Our buried-oxide simulation was intended as a controlled proxy to isolate the effect of introducing a metal-substrate interface in place of an oxidized sidewall. In the revised manuscript, we will expand the discussion to provide explicit justification for this approach, including estimates of electric-field participation ratios for the buried layer versus native oxide and a note on potential differences in TLS density. We will also clarify the limitations of the proxy while maintaining that the observed improvement is consistent with a reduced surface participation ratio in the damascene devices. revision: partial

Circularity Check

0 steps flagged

No circularity; purely experimental comparison with no derivations or fitted predictions

full rationale

The manuscript reports fabrication and measurement of tantalum damascene CPW resonators versus standard devices, with the key observation being a modest improvement interpreted as suggestive of lower surface participation ratio via buried-oxide simulation of sidewall oxidation. No equations, parameter fits, uniqueness theorems, ansatzes, or self-citations appear in the provided text or abstract. The central claim is an empirical result whose validity rests on the physical assumption that the buried layer proxies native sidewall oxide loss, but this assumption is external to any derivation chain and does not reduce to the inputs by construction. The work is therefore self-contained experimental evidence with no load-bearing steps that loop back on themselves.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The work rests on the domain assumption that surface oxides are a dominant loss channel; no free parameters or new entities are introduced.

axioms (1)
  • domain assumption Surface oxides contribute to losses in superconducting transmon devices
    Opening sentence of the abstract states this as established background.

pith-pipeline@v0.9.0 · 5429 in / 1015 out tokens · 48355 ms · 2026-05-09T21:14:23.467158+00:00 · methodology

discussion (0)

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