arxiv: 2605.07936 · v1 · submitted 2026-05-08 · 📡 eess.SP

Recognition: no theorem link

A Fully Tunable Ultra-Low Power Current-Mode Memory Cell in Standard CMOS Technology

Arthur Fyon , Loris Mendolia , Jean-Michel Redout\'e , Alessio Franci , Guillaume Drion

Authors on Pith no claims yet

Pith reviewed 2026-05-11 03:12 UTC · model grok-4.3

classification 📡 eess.SP

keywords current-mode memoryultra-low power CMOStunable circuitSchmitt triggerneuromorphic hardwarespike encodingbistable memory cellanalog logic

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The pith

A nine-transistor current-mode circuit offers full tunability and nanowatt power consumption in standard CMOS technology.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces a memory cell that operates solely with currents using nine transistors arranged in a feedback setup. It makes three main settings adjustable through separate bias currents while keeping power use very low and performance stable as temperature varies. This matters because it could provide a simple building block for analog systems that need to hold states with little energy and without custom manufacturing steps. The authors also show how the cell supports logic functions based on spikes and memory units for neural-like networks.

Core claim

The central claim is that a unipolar memory cell built from nine standard MOSFET transistors can produce tunable bistable behavior entirely in the current domain. A new feedback arrangement between two thresholding elements allows the threshold current, the width of the hysteresis, and the output gain to be set independently. Simulations in a 180 nanometer process confirm that the cell maintains robust switching even when device parameters vary and that power stays in the nanowatt range with good temperature stability.

What carries the argument

The feedback configuration between two interdependent thresholding elements for producing tunable bistable switching

Load-bearing premise

Schematic simulations of the circuit in a 180 nanometer CMOS process will accurately reflect the performance of a real fabricated version, especially regarding hysteresis behavior, temperature stability, and tolerance to device mismatches.

What would settle it

Experimental results from a silicon prototype fabricated in 180 nanometer CMOS that measure the actual hysteresis width, power consumption under different temperatures, and consistency across multiple instances to check against the simulation predictions.

Figures

Figures reproduced from arXiv: 2605.07936 by Alessio Franci, Arthur Fyon, Guillaume Drion, Jean-Michel Redout\'e, Loris Mendolia.

**Figure 1.** Figure 1: Conceptual architecture of the proposed dual-Heaviside feedback Schmitt trigger, along with the electronic schematics of the individual Heaviside circuit and the full Schmitt trigger. The hysteresis behavior arises naturally from the feedback current Iwidth, which lowers the effective input threshold to Ithresh − Iwidth, thus enabling bistability. The three control parameters Ithresh, Igain, and Iwidth are… view at source ↗

**Figure 2.** Figure 2: A. Transient simulation of the proposed Schmitt trigger under triangular input current for different operating temperatures. B. DC sweep demonstrating hysteretic behavior for different operating temperatures. C. Monte Carlo analysis of the proposed Schmitt trigger in DC input sweep analysis with 3σ process variation at room temperature. Baseline parameters: Igain = 486 pA, Ithresh = 368 pA, and Iwidth = 21… view at source ↗

**Figure 3.** Figure 3: A. Igain DC sweep analysis from 0 to 500 pA of the proposed Schmitt trigger for different operating temperatures. B. Ithresh DC sweep analysis from 100 pA to 400 pA of the proposed Schmitt trigger for different operating temperatures with Iwidth = 50 pA. C. Iwidth DC sweep analysis from 10 pA to 300 pA of the proposed Schmitt trigger for different operating temperatures. Baseline parameters: Igain = 486 pA… view at source ↗

**Figure 4.** Figure 4: Circuit implementation of the XOR logic gate using the proposed Schmitt trigger. Each input is processed by both a standard and an inverted Schmitt trigger to detect spike polarity. The outputs are summed and thresholded to produce the XOR operation. The other four logic gates (AND, OR, NAND, NOR) follow analogous configurations with different summation and threshold arrangements. For the AND gate, Ist1 an… view at source ↗

**Figure 5.** Figure 5: Simulation results of all five spike-based logic gates (AND, NAND, OR, NOR, XOR) for different input spike polarity combinations (top). The three-level current encoding (0 pA = logic 0 / negative spike, 250 pA = undefined / no spike received, 500 pA = logic 1 / positive spike) enables bidirectional logic operations while maintaining the unipolar current constraint. Each gate correctly responds to the polar… view at source ↗

read the original abstract

This work introduces a fully tunable, ultra-low power unipolar memory cell inspired by the Schmitt-trigger comparator and designed in CMOS using only nine transistors. The proposed circuit operates entirely in the current domain and exploits a novel feedback configuration between two interdependent Heaviside-like thresholding elements to produce tunable bistable switching behavior. Its three key parameters-threshold current, hysteresis width, and output gain-are independently tunable via programmable bias currents, enabling flexibility across diverse analog computing applications. Unlike prior Schmitt-trigger designs, it simultaneously achieves current-mode operation, nanowatt-range power consumption, temperature stability, and full tunability, solely using standard MOSFET elements. Schematic-level simulations in a 180 nm CMOS process confirm robust hysteresis and resilience to device mismatch. Building on this circuit, we develop a complete family of spike-based logic gates using three-level current encoding, where the bistable memory retains the polarity of the last spike on each input indefinitely, enabling asynchronous logic operations without temporal windowing or refresh mechanisms. The same circuit also serves as the primitive for Bistable Memory Recurrent Units in analog neural networks, where the quantized hidden states provide inherent noise immunity. Together, these capabilities position the design as a versatile building block for next-generation neuromorphic processors integrating memory, logic, and recurrent computation.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

A new nine-transistor current-mode bistable cell with independent tunability of threshold, hysteresis and gain, but all evidence is schematic simulation only.

read the letter

The main thing to know is that this paper gives a concrete nine-transistor current-mode memory cell whose threshold current, hysteresis width, and output gain can each be set separately by bias currents. The circuit uses a feedback loop between two interdependent Heaviside-like elements to get bistable behavior in the current domain at nanowatt power, and the authors show how the same block can serve as the core for spike-based logic gates and for bistable memory recurrent units in analog networks. That topology and the three-level current encoding look like genuine extensions of standard Schmitt-trigger ideas, and the schematic results in 180 nm CMOS appear consistent with the claimed hysteresis and basic mismatch tolerance. The work is therefore useful to anyone who needs a compact, tunable analog memory primitive for neuromorphic hardware. The clear limitation is that every performance claim rests on schematic-level simulations. No post-layout extraction, no Monte Carlo runs across corners, and no silicon measurements are presented. At nanowatt currents even modest interconnect capacitance or local temperature gradients can shift the effective switching points, so the asserted temperature stability and mismatch resilience remain untested in conditions that matter. The abstract states the simulations confirm robustness, but without those extra checks the gap between schematic and fabricated behavior is still open. This paper is aimed at analog circuit designers working on low-power neuromorphic processors. Readers who build or evaluate current-mode building blocks will find the topology and the logic-gate examples worth examining. I would send it for peer review. The idea is specific enough and the simulations give reviewers something concrete to assess, even if they will almost certainly request layout and measurement data.

Referee Report

2 major / 0 minor

Summary. The manuscript introduces a nine-transistor current-mode unipolar memory cell in standard CMOS technology, inspired by the Schmitt-trigger comparator. It employs a novel feedback configuration between two interdependent Heaviside-like thresholding elements to achieve bistable switching, with independent tunability of threshold current, hysteresis width, and output gain via programmable bias currents. The design claims nanowatt-range power consumption, temperature stability, and resilience to device mismatch, supported by schematic-level simulations in a 180 nm CMOS process. Applications include spike-based logic gates using three-level current encoding and Bistable Memory Recurrent Units for analog neural networks.

Significance. If the performance claims hold under fabricated conditions, the circuit would provide a versatile, low-power tunable memory primitive suitable for neuromorphic processors, enabling asynchronous spike-based logic without temporal windowing or refresh and offering inherent noise immunity in recurrent neural units. The combination of current-mode operation, full independent tunability, and ultra-low power using only standard MOSFETs would distinguish it from prior Schmitt-trigger designs and support integration of memory, logic, and computation in analog systems.

major comments (2)

[Abstract] Abstract: The statement that 'schematic-level simulations in a 180 nm CMOS process confirm robust hysteresis and resilience to device mismatch' lacks supporting evidence on the simulation setup. No indication is given of post-layout parasitic extraction, Monte Carlo analysis across process corners for mismatch, or temperature corner simulations, all of which are critical at nanowatt current levels where interconnect parasitics and well-proximity effects can alter feedback thresholds and degrade bistability.
[Abstract] Abstract: The central claim that the nine-transistor cell 'simultaneously achieves current-mode operation, nanowatt-range power consumption, temperature stability, and full tunability' rests on the assumption that schematic simulations accurately predict fabricated behavior. Schematic-level analysis omits layout-dependent effects such as parasitic capacitances and local heating, which can shift effective switching thresholds and undermine the claimed temperature-stable Heaviside-like operation and mismatch resilience.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback highlighting the need for clearer simulation details and more qualified claims in the abstract. We address each point below and will revise the manuscript accordingly.

read point-by-point responses

Referee: [Abstract] Abstract: The statement that 'schematic-level simulations in a 180 nm CMOS process confirm robust hysteresis and resilience to device mismatch' lacks supporting evidence on the simulation setup. No indication is given of post-layout parasitic extraction, Monte Carlo analysis across process corners for mismatch, or temperature corner simulations, all of which are critical at nanowatt current levels where interconnect parasitics and well-proximity effects can alter feedback thresholds and degrade bistability.

Authors: We agree that the abstract would benefit from additional context on the simulation methodology. In the revised manuscript we will expand the abstract and add a short simulation setup paragraph describing the use of the typical-typical corner in the 180 nm PDK, nominal 27 °C temperature, DC sweep and transient analyses with the listed bias currents, and targeted parameter sweeps to illustrate mismatch tolerance. We did not perform post-layout extraction, Monte Carlo statistical runs, or multi-corner temperature simulations because the work is presented at the schematic level to establish the circuit concept. We will explicitly qualify the abstract statement to read “schematic-level simulations … confirm …” and note the absence of layout-dependent effects as a limitation for future fabrication. revision: partial
Referee: [Abstract] Abstract: The central claim that the nine-transistor cell 'simultaneously achieves current-mode operation, nanowatt-range power consumption, temperature stability, and full tunability' rests on the assumption that schematic simulations accurately predict fabricated behavior. Schematic-level analysis omits layout-dependent effects such as parasitic capacitances and local heating, which can shift effective switching thresholds and undermine the claimed temperature-stable Heaviside-like operation and mismatch resilience.

Authors: The referee correctly notes that schematic results cannot fully capture layout parasitics or self-heating. We will revise the abstract to replace the unqualified claim with “schematic-level simulations indicate that the cell simultaneously achieves …” and will add a brief discussion paragraph acknowledging that interconnect capacitance and local heating may affect thresholds in a fabricated implementation. Temperature stability was verified only through schematic sweeps at 0 °C, 27 °C and 80 °C; we will report these specific conditions and state that full temperature-corner and post-layout validation remain future work. The core circuit topology and tunability results are unaffected by this clarification. revision: partial

Circularity Check

0 steps flagged

No significant circularity in circuit design or simulation-based claims

full rationale

The paper proposes an original nine-transistor current-mode Schmitt-trigger-inspired memory cell whose three tunable parameters are set directly by independent bias currents. All performance assertions (nanowatt power, temperature stability, mismatch resilience, bistable hysteresis) are supported by schematic-level simulations in 180 nm CMOS rather than by any closed mathematical derivation. No equations, fitted parameters renamed as predictions, self-definitional loops, or load-bearing self-citations appear in the provided text. The design choices and simulation results constitute independent content; the validation step does not reduce to the inputs by construction. This is the expected non-finding for a circuit-topology paper whose central claims rest on external simulation evidence.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The design relies on established CMOS transistor models and simulation assumptions rather than new physical principles or fitted parameters; no new entities are postulated.

axioms (1)

domain assumption Standard MOSFET models and simulation tools for 180 nm CMOS process accurately represent circuit behavior
All performance claims including tunability and stability are based on these models.

pith-pipeline@v0.9.0 · 5538 in / 1242 out tokens · 41731 ms · 2026-05-11T03:12:26.264435+00:00 · methodology

discussion (0)

Reference graph

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