arxiv: 2605.09142 · v1 · submitted 2026-05-09 · 🪐 quant-ph

Recognition: no theorem link

DART-Q : A Deadline-Driven Framework for Real-Time QLDPC Decoding

Ameya S. Bhave , Navnil Choudhury , Kanad Basu

Authors on Pith no claims yet

Pith reviewed 2026-05-12 02:17 UTC · model grok-4.3

classification 🪐 quant-ph

keywords quantum error correctionQLDPCreal-time decodingdeadline schedulingdecoder frameworktail latencymemory constraints

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The pith

DART-Q framework shows real-time QLDPC decoding viability is governed by state organization, overload policy, and service capacity.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces DART-Q to model quantum error correction decoding as deadline-driven jobs with queuing and earliest-deadline-first scheduling. It studies how memory constraints, admission control, and service capacity affect timely decoding for QLDPC codes under time-varying load. Simulations show a cached-summary state organization reduces the SRAM-fit boundary by 4x versus edge-centric designs. Doubling decoder capacity cuts the miss rate from 97.64% to 0.98% and p99 latency from 3.861 ms to 10 μs, while relaxing backlog caps under overload increases queued work by 20.1x and worsens latency by 17.6x with little throughput gain.

Core claim

Real-time decoder viability for QLDPC codes is governed by state organization, overload policy, and service capacity. A cached-summary state organization lowers the SRAM-fit boundary by 4x relative to an edge-centric baseline. Relaxing the backlog cap under overload increases queued work by 20.1x and worsens p99 latency by 17.6x with minimal throughput gain, while doubling decoder capacity reduces MissRate from 97.64% to 0.98% and improves p99 latency from 3.861ms to 10μs.

What carries the argument

DART-Q models each decode request as a deadline-driven online service job with queueing, non-preemptive Earliest Deadline First scheduling, configurable admission control, service times, and bounded rescue policies.

Load-bearing premise

The controlled simulation studies accurately capture the timing, memory, and workload characteristics of real quantum hardware and decoder implementations under time-varying load.

What would settle it

Running identical workload traces on physical quantum hardware with a real-time decoder and checking whether observed miss rates and p99 latencies match the simulated values under the same overload conditions.

Figures

Figures reproduced from arXiv: 2605.09142 by Ameya S. Bhave, Kanad Basu, Navnil Choudhury.

**Figure 2.** Figure 2: Real-time decoding as a service. A streaming syndrome [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗

**Figure 3.** Figure 3: DART-Q architecture and measurement flow. Raw detector-event traces are released as [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗

**Figure 4.** Figure 4: Traffic model and SRAM-capacity knee. (a) Decoder [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗

**Figure 5.** Figure 5: Off-chip traffic per decode job versus on-chip SRAM budget for edge-centric state and cached summaries across BB72, [PITH_FULL_IMAGE:figures/full_fig_p008_5.png] view at source ↗

**Figure 6.** Figure 6: Tail-latency behavior under bounded mitigation policies. The three panels show p99 response time, MissRate, and rescue [PITH_FULL_IMAGE:figures/full_fig_p009_6.png] view at source ↗

**Figure 7.** Figure 7: QoS shaping and capacity scaling in the overloaded regime. Top-level admission control trades drops against deadline [PITH_FULL_IMAGE:figures/full_fig_p010_7.png] view at source ↗

read the original abstract

Real-time quantum error correction places the classical decoder inside the fault-tolerant control loop under strict timing and memory constraints. For quantum low-density parity-check (QLDPC) codes, practical deployment therefore depends not only on correction performance, but also on timely decoding under deadlines, finite on-chip memory, and time-varying load. However, existing decoder studies primarily emphasize correction performance without exposing operational viability under these constraints. We present DART-Q, a real-time QLDPC decoding framework that treats windowed workloads as discrete arrival, queueing, service, and completion events. DART-Q models each decode request as a deadline-driven online service job with queueing and non-preemptive Earliest Deadline First scheduling. It supports configurable admission control, service times, and bounded rescue policies. Through controlled studies of the SRAM-fit transition, tail latency, overload, and a capacity-scaling extension, DART-Q isolates the effects of memory pressure, rescue selectivity, admission control, and pooled service capacity on timely decoding. Our results show that real-time decoder viability is governed by state organization, overload policy, and service capacity. A cached-summary state organization lowers the SRAM-fit boundary by 4x relative to an edge-centric baseline. Under overload, relaxing the backlog cap increases queued work by approximately 20.1x and worsens p99 latency by approximately 17.6x, with little gain in useful throughput. In contrast, doubling decoder capacity reduces the MissRate from 97.64% to 0.98% and improves p99 latency from 3.861ms to 10$\mu$s. These results position DART-Q as a framework for exposing the regime changes that determine real-time QLDPC decoder viability under deadlines, finite memory, and time-varying load.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

DART-Q is a simulation framework for deadline-driven QLDPC decoding that surfaces useful operational tradeoffs, but its numbers rest on uncalibrated service times and workloads.

read the letter

The paper introduces DART-Q, a discrete-event model that treats windowed QLDPC decoding as arrival, queueing, and non-preemptive EDF-scheduled jobs. It runs controlled experiments on state organization, backlog caps, admission control, and pooled capacity to see what keeps decoders under deadlines and within SRAM limits. This is new: prior work on QLDPC mostly stops at correction performance, while this one isolates how memory layout and overload policy shift the feasible regime. The reported effects are concrete, such as the cached-summary organization moving the SRAM-fit boundary by 4x and capacity doubling dropping miss rate from 97.64% to 0.98% with much better tail latency. Those directional findings are the part worth keeping. The limitation is that all the multipliers and thresholds come from configurable service-time distributions and synthetic workloads. Nothing in the description shows these were fitted to measured FPGA or ASIC runtimes, syndrome processing delays, or actual time-varying error rates. If the assumed service times are off by even a modest factor, the exact claims about 20x queued work or microsecond p99 latencies become illustrative rather than predictive. This is aimed at people building real-time quantum control hardware who need to reason about scheduling and memory alongside the code itself. A reader in that group can extract the modeling structure and rerun the studies with their own traces. I would send it for peer review. The topic matters for fault-tolerant systems and the framework is a reasonable starting point, but reviewers should require calibration data or sensitivity analysis on the timing parameters.

Referee Report

1 major / 1 minor

Summary. The manuscript introduces DART-Q, a deadline-driven framework for real-time QLDPC decoding that models windowed workloads as discrete arrival, queueing, service, and completion events under non-preemptive Earliest Deadline First scheduling. It supports configurable admission control, service times, and rescue policies, and uses controlled simulation studies to isolate effects of state organization (cached-summary vs. edge-centric), overload policies (backlog cap), and decoder capacity on metrics including SRAM-fit boundary, queued work, MissRate, and p99 latency, reporting outcomes such as a 4x SRAM-fit boundary reduction and MissRate drop from 97.64% to 0.98% upon capacity doubling.

Significance. If the underlying simulation model is shown to be representative, the work could be significant for quantum error correction by providing a structured way to evaluate operational constraints (deadlines, memory, time-varying load) that are often secondary to correction performance in existing studies. The framework's ability to expose regime changes via configurable policies is a methodological strength, though its value hinges on the fidelity of the service-time and workload assumptions.

major comments (1)

[Controlled studies of SRAM-fit transition, tail latency, overload, and capacity-scaling extension (as described in the 3] The headline quantitative results (4x SRAM-fit boundary reduction, 20.1x queued-work increase, 17.6x p99 latency worsening, MissRate reduction from 97.64% to 0.98%, p99 latency improvement to 10μs) are produced entirely by the discrete-event simulator with configurable service times and workload traces. No calibration or validation of these parameters against measured runtimes, memory access patterns, or syndrome processing latencies of actual QLDPC decoders on FPGA/ASIC hardware is provided, rendering the mapping from simulated regime changes to physical real-time viability unanchored. This is load-bearing for all claims about decoder viability under deadlines and finite memory.

minor comments (1)

[Abstract] The abstract reports specific numerical factors (e.g., 'approximately 20.1x') without accompanying details on simulation run count, statistical significance, or sensitivity analysis; these should be added to the results section for reproducibility.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for their constructive review and for highlighting the importance of validating the simulation assumptions against hardware measurements. We address the major comment in detail below, proposing targeted revisions to clarify the scope and limitations of our results.

read point-by-point responses

Referee: The headline quantitative results (4x SRAM-fit boundary reduction, 20.1x queued-work increase, 17.6x p99 latency worsening, MissRate reduction from 97.64% to 0.98%, p99 latency improvement to 10μs) are produced entirely by the discrete-event simulator with configurable service times and workload traces. No calibration or validation of these parameters against measured runtimes, memory access patterns, or syndrome processing latencies of actual QLDPC decoders on FPGA/ASIC hardware is provided, rendering the mapping from simulated regime changes to physical real-time viability unanchored. This is load-bearing for all claims about decoder viability under deadlines and finite memory.

Authors: We agree that direct calibration to hardware measurements would provide stronger anchoring for the quantitative claims. However, as real-time QLDPC decoding under strict deadlines is not yet implemented on FPGA or ASIC hardware in the literature, comprehensive profiling data for service times, memory access patterns, and syndrome latencies in a deadline-driven setting is unavailable. DART-Q is presented as a simulation framework to systematically explore how factors such as state organization, overload policies, and service capacity affect deadline compliance in windowed workloads. The reported outcomes illustrate the sensitivity of the system to these parameters and the existence of regime changes (e.g., the SRAM-fit boundary shift with cached-summary organization). To strengthen the manuscript, we will revise the introduction and results sections to more explicitly frame the results as demonstrating relative effects under configurable parameters, add a new subsection on 'Parameterization and Validation' that discusses how service times can be derived from hardware benchmarks or published decoder runtimes, and include a limitations paragraph acknowledging the current lack of end-to-end hardware validation. These changes will better position the work as a tool for guiding future hardware-aware studies rather than claiming direct physical predictions. revision: partial

Circularity Check

0 steps flagged

No significant circularity; results are direct simulation outputs

full rationale

The paper presents DART-Q as a discrete-event simulation framework modeling decode requests as deadline-driven jobs with configurable service times, state organizations, admission control, and EDF scheduling. All reported quantitative outcomes (4x SRAM-fit reduction, 20.1x queued-work increase, MissRate drop from 97.64% to 0.98%, p99 latency to 10μs) are produced by running the model under controlled parameter sweeps rather than by any equation, fitted parameter, or self-citation that reduces to its own inputs. No mathematical derivations, uniqueness theorems, or ansatzes appear in the text; the work is self-contained as an empirical modeling study whose claims rest on the explicit simulation configuration, not on circular re-derivation of those configurations.

Axiom & Free-Parameter Ledger

3 free parameters · 2 axioms · 1 invented entities

The framework rests on standard queueing and real-time scheduling assumptions plus configurable parameters for service times and policies; no invented physical entities are introduced.

free parameters (3)

service times
Configurable parameter for modeling decode request processing duration.
backlog cap
Configurable limit on queued work under overload that affects latency and throughput.
admission control parameters
Configurable rules for accepting or rejecting decode requests.

axioms (2)

domain assumption Decode requests can be treated as discrete arrival, queueing, service, and completion events
Core modeling choice stated in the abstract for windowed workloads.
domain assumption Non-preemptive Earliest Deadline First scheduling is suitable for the decode jobs
Scheduling policy used in the framework description.

invented entities (1)

DART-Q framework no independent evidence
purpose: To model and study real-time QLDPC decoding under deadlines and memory constraints
Newly presented framework in the paper.

pith-pipeline@v0.9.0 · 5628 in / 1513 out tokens · 52369 ms · 2026-05-12T02:17:00.927848+00:00 · methodology

discussion (0)

Reference graph

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