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arxiv: 2606.21308 · v1 · pith:3OCSFO5Ynew · submitted 2026-06-19 · 🪐 quant-ph

Time-Bin BB84 QKD System Using Indium Phosphide and Silicon Nitride Photonic Integrated Circuits

Denis Fatkhiev , Alexander Grebenchukov , Jo\~ao dos Reis Fraz\~ao , Gleb Nazarikov , Chigo Okonkwo , Idelfonso Tafur Monroy This is my paper

Pith reviewed 2026-06-26 14:14 UTC · model grok-4.3

classification 🪐 quant-ph
keywords quantum key distributionphotonic integrated circuitstime-bin encodingBB84 protocolInP-SiN integrationfinite-key securitycoherent attacks
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The pith

A dual-chip InP-SiN photonic system implements time-bin BB84 QKD with finite-key security and kbps rates over 150-250 km fiber.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes that a combination of indium phosphide and silicon nitride photonic integrated circuits can handle both pulse generation and decoding for time-bin encoded BB84 quantum key distribution entirely on chip. It reports QBER below 4 percent while extracting secret keys at kilobit-per-second rates across long fiber spans, with security proven for finite keys against coherent attacks. A sympathetic reader would care because this moves QKD from bulk optics toward compact, manufacturable hardware that could fit inside existing telecom infrastructure. The demonstration shows that on-chip reconfigurability does not prevent the protocol from meeting the error and distance thresholds needed for practical use.

Core claim

The authors demonstrate a dual-chip InP-SiN photonic QKD system with on-chip pulse generation and reconfigurable decoding that implements time-bin BB84, achieves finite-key security against coherent attacks, maintains QBER below 4 percent, and delivers secret keys at kbps rates over 150-250 km of fiber.

What carries the argument

Dual-chip InP-SiN photonic integrated circuit platform that performs on-chip pulse generation and reconfigurable decoding for time-bin BB84 encoding.

If this is right

  • The same chip platform can support secret-key extraction at kbps rates while meeting finite-key security bounds against coherent attacks.
  • Reconfigurable on-chip decoding allows the system to adapt the time-bin BB84 protocol without external bulk optics.
  • Integration of pulse generation on the InP chip removes the need for off-chip laser sources in the transmitter.
  • The reported distances and error rates indicate compatibility with standard telecom fiber spans.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Further integration of both chips into a single package could reduce alignment losses and improve long-term stability.
  • The approach may extend to other time-bin protocols or to wavelength-multiplexed channels on the same SiN platform.
  • Deployment tests on installed fiber links with active network traffic would reveal whether the measured QBER holds under real-world conditions.

Load-bearing premise

The on-chip pulse generation and reconfigurable decoding introduce no unaccounted losses, timing jitter, or errors beyond those captured in the reported QBER and security analysis.

What would settle it

A measurement in which the system produces QBER above 4 percent or zero positive secret key rate when operated over 150 km of fiber under the reported conditions would falsify the performance claim.

Figures

Figures reproduced from arXiv: 2606.21308 by Alexander Grebenchukov, Chigo Okonkwo, Denis Fatkhiev, Gleb Nazarikov, Idelfonso Tafur Monroy, Jo\~ao dos Reis Fraz\~ao.

Figure 1
Figure 1. Figure 1: (a) System-level schematic showing experimental setup. (b) Microscope image of the InP PIC (Alice). (c) Microscope image of the SiN PIC (Bob). arXiv:2606.21308v1 [quant-ph] 19 Jun 2026 [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Time-bin histograms of the states recorded at the receiver: (a) Z0 and (b) Z1 on the Z path, (c) X0 on the Z path, and (d) X0 on the X path, showing destructive interference in the central slot. The green shaded region indicates the active detection time-slot. Z-basis states on the X path are omitted as the single-pulse inputs do not produce interference [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Optimization and performance of the QKD system versus channel loss. (a) Optimal selection probabilities for the Z basis and the signal state. (b) Optimal mean photon numbers of the signal and decoy states. (c) Secret key rate for three values of the sifted Z-basis block size NZ . Panels (a) and (b) are shown for a fixed NZ = 108 . The key is distilled from the sifted Z-basis detections, with its secure len… view at source ↗
read the original abstract

We demonstrate a dual-chip InP-SiN photonic QKD system with on-chip pulse generation and reconfigurable decoding, implementing time-bin BB84 with finite-key security against coherent attacks. The system sustains a QBER below 4% and delivers secret keys at kbps rates over 150-250 km of fiber.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript presents a dual-chip InP-SiN photonic integrated circuit implementation of time-bin BB84 QKD. It claims on-chip pulse generation and reconfigurable decoding, finite-key security against coherent attacks, QBER below 4%, and secret-key rates at kbps levels over 150-250 km of fiber.

Significance. If the experimental characterization and security analysis are complete and the on-chip elements introduce no unmodeled errors, the result would demonstrate a compact, foundry-compatible platform for time-bin QKD that could aid integration and scalability. The finite-key analysis against coherent attacks, if fully detailed, would strengthen the security claim relative to many prior PIC demonstrations.

major comments (2)
  1. [Abstract and §4] Abstract and §4 (Experimental Results): the reported QBER <4% and kbps rates are presented without an accompanying error budget or measured timing jitter/insertion-loss values for the InP pulse generator and SiN decoder; this directly bears on whether the central claim that on-chip components add no unaccounted phase instability or side-channels holds.
  2. [§5] §5 (Security Analysis): the finite-key security proof against coherent attacks is asserted but no outline of the phase-error estimation, decoy-state parameters, or how on-chip reconfigurability affects the single-photon source assumption is supplied; without this the weakest assumption in the stress-test cannot be checked.
minor comments (2)
  1. [Figures 2 and 3] Figure 2 and 3: axis labels and legend entries for the reconfigurable decoder states are difficult to read; add explicit annotations for the time-bin basis projections.
  2. Ensure the fiber lengths (150 km and 250 km) are stated with the corresponding loss values and detection efficiencies in the main text rather than only in supplementary material.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback on our manuscript. We address each major comment below and indicate the revisions made to improve clarity and completeness.

read point-by-point responses

  1. Referee: [Abstract and §4] Abstract and §4 (Experimental Results): the reported QBER <4% and kbps rates are presented without an accompanying error budget or measured timing jitter/insertion-loss values for the InP pulse generator and SiN decoder; this directly bears on whether the central claim that on-chip components add no unaccounted phase instability or side-channels holds.

    Authors: We agree that an explicit error budget strengthens the central claim. In the revised manuscript we have added to §4 a tabulated error budget that includes the measured timing jitter of the InP pulse generator (sub-ps level) and the SiN decoder, together with the insertion-loss values for each on-chip element. These data are used to bound any residual phase instability and to confirm that no unaccounted side-channels are introduced beyond the modeled QBER. The abstract has been updated to reference the error-budget analysis. revision: yes

  2. Referee: [§5] §5 (Security Analysis): the finite-key security proof against coherent attacks is asserted but no outline of the phase-error estimation, decoy-state parameters, or how on-chip reconfigurability affects the single-photon source assumption is supplied; without this the weakest assumption in the stress-test cannot be checked.

    Authors: We acknowledge that the original §5 presented the finite-key result without sufficient intermediate steps. The revised section now supplies (i) the explicit phase-error estimation procedure based on the decoy-state method, (ii) the numerical decoy-state intensities and probabilities used in the experiment, and (iii) a short argument showing that the on-chip reconfigurability (basis selection via the SiN decoder) preserves the Poissonian photon-number statistics of the InP source and therefore does not invalidate the single-photon-source assumption under coherent attacks. revision: yes

Circularity Check

0 steps flagged

No derivation chain; experimental demonstration only.

full rationale

The paper is an experimental report of a dual-chip InP-SiN photonic QKD system implementing time-bin BB84. The abstract and provided text contain no equations, derivations, predictions, or theoretical claims that reduce to fitted parameters or self-referential definitions. Claims rest on measured QBER <4% and observed key rates over fiber spans, which are direct experimental outcomes rather than outputs of any internal derivation. No self-citation load-bearing steps or ansatzes are present in the visible content. This is a standard honest non-finding for a pure experimental paper.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

Abstract-only review yields minimal ledger entries. No free parameters or invented entities are identifiable. The security claim rests on standard QKD assumptions not detailed here.

axioms (1)
  • domain assumption Finite-key security analysis against coherent attacks applies directly to the implemented time-bin BB84 system.
    Abstract states the security level without specifying the proof or assumptions invoked.

pith-pipeline@v0.9.1-grok · 5604 in / 1072 out tokens · 25623 ms · 2026-06-26T14:14:18.886678+00:00 · methodology

discussion (0)

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Reference graph

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