SafeGen: LLM-Driven Assertion Generation and Fault Criticality Evaluation for Functional Safety

Arjun Chaudhuri; Krishnendu Chakrabarty; Rubin Parekhji; Xuanyi Tan

SafeGen: LLM-Driven Assertion Generation and Fault Criticality Evaluation for Functional Safety

T0 review · 1 major / 0 minor · reviewed 2026-06-25 · grok-4.3

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Pith's one-line read SafeGen uses an LLM and Hyper Knowledge Graph to generate design-aware assertions for semantic fault criticality assessment in functional safety.

desk verdict SafeGen ties LLMs to an FMEDA-derived HyperKG for traceable assertion generation and semantic fault grading, but the abstract gives no numbers to back the quality claims. read the letter →

arxiv 2606.25296 v1 pith:X3TK2CBN submitted 2026-06-24 cs.AR

Xuanyi Tan , Arjun Chaudhuri , Rubin Parekhji , Krishnendu Chakrabarty This is my paper · ORCID

classification cs.AR

keywords functionalsafetyassertiongenerationlargelanguagemodelsfaultcriticalityknowledgegraphFMEDAformalverificationautomotivechips

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper introduces SafeGen as an LLM-driven framework assisted by formal verification for assessing fault criticality in automotive chip designs. It builds a document-level Hyper Knowledge Graph incorporating FMEDA guidelines and RTL information to extract verifiable specifications and generate Functional Safety Assertions that are linked to those specs. This allows traceable reasoning and semantic-level grading of faults using formal property verification instead of conservative simulation-based methods. A sympathetic reader would care because accurate fault analysis is essential for safety certification in autonomous systems, where over-conservative assessments can lead to unnecessary design changes.

What carries the argument

The document-level Hyper Knowledge Graph (HyperKG) enriched with FMEDA guidelines and RTL data, which guides LLM generation of specification-linked Functional Safety Assertions (FSAs) for traceable fault assessment.

What would settle it

Demonstration that assertions produced by SafeGen either miss critical faults affecting system safety or incorrectly grade faults due to inaccurate HyperKG enrichment from the documents.

Watch

Extended reading notes

Core claim

SafeGen leverages large language models and a document-level Hyper Knowledge Graph that incorporates Failure Modes, Effects, and Diagnostic Analysis guidelines to extract verifiable specifications from design and safety documents. The graph is enriched with register-transfer-level information to generate Functional Safety Assertions that are semantically grounded and design-aware. Each assertion is linked to its corresponding specification for traceability. A gate-to-RTL fault-mapping mechanism with formal property verification enables semantic-level fault criticality grading based on assertion violations, demonstrated on a field-oriented control system co-simulation platform.

Load-bearing premise

The document-level Hyper Knowledge Graph accurately incorporates FMEDA guidelines and RTL information to produce verifiable specifications and design-aware Functional Safety Assertions.

Editorial extensions

If this is right

Generates higher-quality assertions than existing LLM-based frameworks.
Provides greater semantic interpretability in fault criticality assessment than traditional simulation.
Supports evaluation of both stuck-at and bridging faults via gate-to-RTL mapping.
Enables traceable reasoning throughout the assessment process.
Validated on a digital-physical co-simulation platform for a field-oriented control system.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The method could be adapted for other safety-critical domains like medical devices or aerospace electronics.
Semantic traceability may reduce the time required for safety case documentation and certification.
Further integration with simulation tools could create hybrid analysis workflows that combine semantic and quantitative insights.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Desk Editor's Note

read the letter

The main takeaway is that this paper outlines SafeGen, an LLM-driven pipeline that builds a document-level Hyper Knowledge Graph from FMEDA guidelines and RTL details, then uses it to produce linked Functional Safety Assertions. Those assertions feed into gate-to-RTL fault mapping and formal property verification to grade criticality at the specification level rather than through raw simulation counts. A co-simulation setup on a field-oriented control system is mentioned for validation.

What stands out as new is the explicit semantic linking layer: assertions stay tied back to the original safety specs via the graph, and the fault mapping tries to move beyond module-level conservatism. That combination is not standard in the prior LLM assertion literature referenced.

The work does a solid job framing a practical need in automotive hardware, where traceability matters for certification. The emphasis on design-aware assertions and the gate-to-RTL step shows attention to how faults actually propagate in real designs.

The clearest soft spot is the evaluation. The abstract states that SafeGen produces higher-quality assertions and better interpretability than existing LLM frameworks and simulation-based methods, yet it supplies no metrics, no baseline descriptions, no dataset size, and no error breakdown. Without those, the superiority claim cannot be checked. The HyperKG construction is also described at a high level, so its accuracy and the amount of manual curation required remain unclear.

This paper is aimed at hardware verification and functional-safety teams working on automotive or similar safety-critical chips. Readers already familiar with FMEDA and FPV will see the most direct value in the pipeline description.

It deserves a serious referee. The integration addresses a real gap in traceable analysis, and the problem is important enough that the full experimental section should be reviewed even if revisions are needed on the quantitative side.

Referee Report

1 major / 0 minor

Summary. The manuscript presents SafeGen, an LLM-driven framework for functional safety-oriented fault criticality assessment in automotive chip design. It constructs a document-level Hyper Knowledge Graph (HyperKG) that incorporates FMEDA guidelines to extract verifiable specifications from design and safety documents, enriches it with RTL information to generate specification-linked Functional Safety Assertions (FSAs), applies gate-to-RTL fault mapping for stuck-at and bridging faults, and uses formal property verification (FPV) for semantic-level grading of fault criticality. Validation occurs via a digital-physical co-simulation platform on a field-oriented control (FOC) system. The central claim is that SafeGen produces higher-quality assertions than existing LLM-based frameworks and greater semantic interpretability than traditional simulation-based methods.

Significance. If the experimental results hold, the framework could improve functional safety analysis by replacing overly conservative module-level simulation with traceable, design-aware assertions that link faults directly to system-level specifications. The emphasis on semantic interpretability and specification traceability addresses a practical gap in automotive safety workflows.

major comments (1)

[Abstract] Abstract: The claim that 'Experimental results demonstrate that SafeGen generates higher-quality assertions than existing LLM-based assertion generation frameworks while providing greater semantic interpretability in fault criticality assessment compared with traditional simulation-based approaches' is unsupported by any quantitative metrics, baseline descriptions, dataset details, or error analysis in the provided text. This absence makes the central experimental claim impossible to evaluate.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive feedback on the abstract. We address the concern point-by-point below and will revise the manuscript accordingly to strengthen the presentation of our experimental claims.

read point-by-point responses

Referee: [Abstract] Abstract: The claim that 'Experimental results demonstrate that SafeGen generates higher-quality assertions than existing LLM-based assertion generation frameworks while providing greater semantic interpretability in fault criticality assessment compared with traditional simulation-based approaches' is unsupported by any quantitative metrics, baseline descriptions, dataset details, or error analysis in the provided text. This absence makes the central experimental claim impossible to evaluate.

Authors: We agree that the abstract, in its current form, presents a high-level summary of the results without embedding the supporting quantitative details. The full manuscript contains dedicated experimental sections that include quantitative metrics (e.g., assertion correctness, coverage, and relevance scores), baseline comparisons against prior LLM-based frameworks, dataset descriptions from the FOC system and FMEDA documents, and error analysis. To make the central claim directly evaluable from the abstract itself, we will revise the abstract to concisely incorporate key quantitative highlights, baseline names, and dataset references while preserving its length constraints. This revision will be made in the next version of the manuscript. revision: yes

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity in derivation chain

full rationale

The paper describes an engineering pipeline (LLM + document-level HyperKG enriched with FMEDA guidelines and RTL data to generate linked FSAs, followed by gate-to-RTL fault mapping and FPV) whose outputs are validated experimentally via co-simulation on an FOC system. No equations, fitted parameters, or quantitative predictions appear; claims of higher-quality assertions rest on direct comparison to baselines rather than any reduction of results to self-referential inputs. No self-citation load-bearing steps, uniqueness theorems, or ansatzes are invoked. The derivation is therefore self-contained as a traceable methodology without circular reduction.

Assumptions & free parameters 0 free parameters · 1 assumptions · 2 invented entities

Abstract-only review prevents full audit; framework introduces HyperKG and FSAs as core components without external validation of their construction accuracy.

assumptions (1)

domain assumption FMEDA guidelines provide a reliable basis for extracting verifiable safety specifications from design documents
Invoked when the HyperKG is built to incorporate FMEDA guidelines

invented entities (2)

Hyper Knowledge Graph (HyperKG)
purpose: Store and link FMEDA guidelines with RTL information to guide FSA generation
New structure introduced in the framework description
Functional Safety Assertions (FSAs)
purpose: Semantically grounded, traceable assertions for fault criticality evaluation
Generated component central to the assessment process

how reviews work

0 comments

Cite this review

Pith. "Pith review of SafeGen: LLM-Driven Assertion Generation and Fault Criticality Evaluation for Functional Safety." pith.science (2026). https://pith.science/paper/X3TK2CBN

@misc{pith2026260625296,
  author       = {Pith},
  title        = {Pith review of: SafeGen: LLM-Driven Assertion Generation and Fault Criticality Evaluation for Functional Safety},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/X3TK2CBN}},
  note         = {Machine review of arXiv:2606.25296}
}

read the original abstract

With advances in autonomous driving and electric vehicle technologies, functional safety has become a critical requirement in automotive chip design. Traditional simulation-based fault analysis is often overly conservative at the module level and fails to accurately reflect fault criticality. This paper presents SafeGen, an LLM-driven, formal-verification-assisted framework for functional-safety-oriented fault criticality assessment. SafeGen leverages large language models (LLMs) and a document-level Hyper Knowledge Graph (HyperKG) that incorporates Failure Modes, Effects, and Diagnostic Analysis (FMEDA) guidelines to extract verifiable specifications from design and safety documents and evaluate their relevance to overall system safety. The HyperKG is further enriched with register-transfer-level (RTL) information to guide the generation of Functional Safety Assertions (FSAs) that are both semantically grounded and design-aware. Each assertion is linked to its corresponding specification, enabling traceable reasoning throughout the assessment process. A gate-to-RTL fault-mapping mechanism supporting both stuck-at and bridging faults, combined with formal property verification (FPV), enables semantic-level fault criticality grading based on specification-linked assertion violations. A digital-physical co-simulation platform for a field-oriented control (FOC) system is developed to validate SafeGen. Experimental results demonstrate that SafeGen generates higher-quality assertions than existing LLM-based assertion generation frameworks while providing greater semantic interpretability in fault criticality assessment compared with traditional simulation-based approaches.

Figures

Figures reproduced from arXiv: 2606.25296 by the authors.

**Figure 2.** Assertion generation and gate-level fault criticality evaluation. [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗

**Figure 3.** Alignment between document HyperKG and RTL [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗

Figures from the paper (3 more)

**Figure 5.** Figure 5: FOC design for driving a PMSM [41] [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]

**Figure 6.** Figure 6: Closed-loop simulation of the FOC system. [PITH_FULL_IMAGE:figures/full_fig_p005_6.png]

**Figure 7.** Figure 7: Fault criticality distribution of bridging faults (a) [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

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Pith tools

Reviewed June 25, 2026 · model on record in the stance chip above.

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2022