Paper Citation Record · LEDGER

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation

As of 9 August 2026, this Paper Citation Record lists 40 of 40 outbound references and 0 inbound Pith citation observations for arXiv:2607.13079.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2607.13079 v2

Coverage vector

measured 40 of 40 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-02T07:12:19.873246Z

measured 40 of 40 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-09T06:31:02.800959+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

40 of 40 outbound references displayed

verified exact0
verified fuzzy0
unresolved40
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 2e52ec17-7795-4140-910b-62c581128177 · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 1

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:16.462528Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 1b863c95-9662-41bb-b8a8-8137e232cc6f · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 2

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:16.518128Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation c2f9e7a1-61fb-4ff9-b895-7de8b0f47c71 · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 3

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:16.574103Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 9a1e0a4d-0af1-487b-8d07-788be4abbd27 · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 4

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:16.589226Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 5f4185d8-52df-4d8d-ab3d-4ee96782b3f6 · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 5

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:16.649123Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 3ee96091-829c-4fc1-914e-68825b615722 · outbound

This paper cites OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 6

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:16.727289Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 2d59a4ca-7f36-482e-b393-9c617870f6d6 · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:16.820988Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 360329f0-ddec-4902-8442-1b74967c8651 · outbound

This paper cites A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:16.918016Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 7597c667-dc5c-47ac-8d42-2d3e5f4c3269 · outbound

This paper cites RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs

Reference 9

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:17.009828Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 79ef44dc-f4ff-40cf-a701-821b8dae72e7 · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:17.108302Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a2930402-d843-4395-a332-61dbcdc9a790 · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 11

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:17.241884Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 314d27c5-5991-4faf-ace8-4653718b0e80 · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 12

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:17.310205Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 8f343aee-c1a2-42ce-9d33-d1036b725444 · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 13

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:17.504794Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f1ef9766-789f-4c0e-b14b-f8402511baf7 · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 14

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:17.579235Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 1105e949-5463-44b4-baeb-bb091d87e7a3 · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 15

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:17.643304Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 20aaeef2-458d-4eed-a4cd-574e5b8375dd · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 16

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:17.703176Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 6d8e2632-eb25-4f50-ae7a-eabd3b59c0e8 · outbound

This paper cites BetterV: Controlled Verilog Generation with Discriminative Guidance.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 17

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:17.766837Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation c54ee891-db8a-4e77-9d1d-edc26fd2d2d5 · outbound

This paper cites Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification

Reference 18

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:17.834017Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b9412d06-b5b2-49e8-b07d-45d03a4f9c68 · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 19

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:17.899476Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation cd1b59db-98e2-4e10-964d-6ad6cb94c4f8 · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 20

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:17.963561Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 2fc94877-60df-443b-98a2-571a69580b3c · outbound

This paper cites AutoChip: Automating HDL Generation Using LLM Feedback.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation AutoChip: Automating HDL Generation Using LLM Feedback

Reference 21

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:18.056245Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation c1f2c0c2-1fa6-4e1f-a3eb-4177b08feeb7 · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 22

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:18.157849Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 18dbc46f-5b14-40e0-8494-9d25e3cde02f · outbound

This paper cites HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions

Reference 23

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:18.223452Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 7e2a4d32-8b81-4ae0-ad40-1dd46f96a0ad · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 24

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:18.351888Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ba79b26c-24c8-4fcd-a71f-82206005d445 · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:18.508423Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a05f18b2-0553-44ce-9f84-818d1e2520fd · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 26

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:18.706787Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b8d7066f-865f-4fb5-bc97-ee10f77e8a17 · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 27

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:18.870497Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 7c6a4f6d-38f0-4e85-9152-405c4d82d9b4 · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 29

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:18.990637Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 7f7ec560-e2e6-4ca4-9498-642dee57400b · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 30

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:19.052736Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 20e8f4ee-d098-454a-aba4-4c1ff204dca4 · outbound

This paper cites ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Conference’17, July 2017, Washington, DC, USA.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Conference’17, July 2017, Washington, DC, USA

Reference 31

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:19.112195Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f1891a2a-1b4e-4842-9c0d-7c474fc5a7cd · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 32

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:19.192673Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ea42e136-696a-44f2-b602-74bb73d0213d · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 33

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:19.250643Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation c2bf4c4f-fa37-496c-86a2-ce9eac7149eb · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 34

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:19.364858Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 8a936d58-72f3-4f9f-8c52-e4ad4689405e · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 35

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:19.456099Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 28a50ba5-77b8-43d0-804b-9561b1cc934e · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 36

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:19.544186Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a1e7f195-c483-4a88-8ef9-2f725db3b0fb · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 37

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:19.605147Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 8fd225c0-3d78-4064-ba0c-c693909a0c28 · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 38

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:19.660434Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 7fbda8b5-5e47-49f1-9138-c71e7ce9e048 · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 39

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:19.746693Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 636536d8-ce25-47fd-a27c-5a1e0a99dd7f · outbound

This paper cites an unresolved cited work.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Unresolved cited work

Reference 40

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:19.873246Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a4b3e303-884a-442a-b8a3-0624beb2dea9 · outbound

This paper cites In2024 IEEE LLM Aided Design Workshop (LAD).

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation In2024 IEEE LLM Aided Design Workshop (LAD)

Reference 2024

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:17.405894Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Pith citing papers

No inbound Pith citation observations are available.