Paper Citation Record · LEDGER

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis

As of 17 August 2026, this Paper Citation Record lists 37 of 37 outbound references and 0 inbound Pith citation observations for arXiv:2607.15782.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2607.15782 v1

Coverage vector

measured 37 of 37 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-01T22:23:40.608907Z

measured 37 of 37 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-17T06:30:58.91139+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

37 of 37 outbound references displayed

verified exact6
verified fuzzy0
unresolved29
parse uncertain0
malformed identifier2
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation dbb1010b-1d82-43e5-809c-8912a8967487 · outbound

This paper cites Differential Power Analysis,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Differential Power Analysis,

Reference 1

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:37.976077Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 8d03e321-546b-444d-b14f-dff75b441fb1 · outbound

This paper cites Electromagnetic Analysis: Concrete Results,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Electromagnetic Analysis: Concrete Results,

Reference 2

Resolution: verified exact; doi, observed 2026-08-01T22:28:34.234819Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 74e0f170-15b2-42c9-a28c-a62b4d3b96c8 · outbound

This paper cites Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems,

Reference 3

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:38.211184Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 09e18f00-56cb-463c-a5e3-1dcbfecc3359 · outbound

This paper cites EUCLEAK.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis EUCLEAK

Reference 4

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:38.388224Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation d5adb7f7-fe8f-4313-ba99-ed374f1ec3ff · outbound

This paper cites Side-Channel Resis - tance.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Side-Channel Resis - tance

Reference 5

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:38.473627Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 52760291-24dd-4809-84c0-7388abaab8fb · outbound

This paper cites A testing methodology for side-channel resistance validation,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis A testing methodology for side-channel resistance validation,

Reference 6

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:38.531326Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 4b060951-4bbf-4db3-a49b-976fdc642d55 · outbound

This paper cites Coco: Co- Design and Co-Verification of Masked Software Implementations on CPUs,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Coco: Co- Design and Co-Verification of Masked Software Implementations on CPUs,

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:38.564084Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation bf1c4b3b-a412-486a-9fd5-37c7248fac61 · outbound

This paper cites Architecture Corre - lation Analysis (ACA): Identifying the Source of Side-channel Leakage at Gate-level.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Architecture Corre - lation Analysis (ACA): Identifying the Source of Side-channel Leakage at Gate-level

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:38.652889Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 46af94f3-54e2-4092-83c5-261eb6d21d99 · outbound

This paper cites Power side-channel leakage assessment and locating the exact sources of leakage at the early stages of ASIC design process,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Power side-channel leakage assessment and locating the exact sources of leakage at the early stages of ASIC design process,

Reference 9

Resolution: verified exact; doi, observed 2026-08-01T22:28:33.974941Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 4358cee0-9453-4cc3-a2fd-890c784e1950 · outbound

This paper cites IEEE standard for Verilog hardware description language (IEEE 1364-2005),.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis IEEE standard for Verilog hardware description language (IEEE 1364-2005),

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:38.773858Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e9b74efa-0efa-4816-843a-84ba4009ffd0 · outbound

This paper cites IEEE Standard for Design and Verification of Low-Power Inte - grated Circuits.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis IEEE Standard for Design and Verification of Low-Power Inte - grated Circuits

Reference 11

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:38.831712Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f60ebff2-9e03-4ba1-8307-73bb808c73ea · outbound

This paper cites FST Format Specification.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis FST Format Specification

Reference 12

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:38.884845Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 346c7160-636b-4642-b3fe-5545685a647e · outbound

This paper cites RTL to transistor level power modeling and estimation techniques for FPGA and ASIC: A survey,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis RTL to transistor level power modeling and estimation techniques for FPGA and ASIC: A survey,

Reference 13

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:38.933395Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 70c08ce5-4e7d-412a-a7df-e42e70333ca9 · outbound

This paper cites Telescope: Top-Down Hierarchical Pre-silicon Side-channel Leakage Assessment in System- on-Chip Design,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Telescope: Top-Down Hierarchical Pre-silicon Side-channel Leakage Assessment in System- on-Chip Design,

Reference 14

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:38.999648Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation c21d0e11-c604-4177-9b69-5e46289efb11 · outbound

This paper cites Successfully attacking masked AES hardware implementations,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Successfully attacking masked AES hardware implementations,

Reference 15

Resolution: verified exact; doi, observed 2026-08-01T22:28:33.784989Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation b0660b41-af42-41c3-8fd5-ad96937bcba9 · outbound

This paper cites Icarus verilog: open-source verilog more than a year later,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Icarus verilog: open-source verilog more than a year later,

Reference 16

Resolution: malformed identifier; no resolver link, observed 2026-08-01T22:23:39.110346Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation fdb8ba95-e158-4736-ae95-e2a04cd5ced8 · outbound

This paper cites Verilator.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Verilator

Reference 17

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:39.209890Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation bb4631ea-97b6-44f7-81fd-e476f8b90d3d · outbound

This paper cites Cocotb: a Python-based digital logic verification frame - work.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Cocotb: a Python-based digital logic verification frame - work

Reference 18

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:39.285358Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 3de49759-b6a4-43c0-9263-2dbcf5fc0247 · outbound

This paper cites Online template attacks,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Online template attacks,

Reference 19

Resolution: malformed identifier; no resolver link, observed 2026-08-01T22:23:39.367616Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b7856683-bc4a-4cee-9c8c-d1a15060ec52 · outbound

This paper cites CVC Verilog Compiler -- Fast Complex Language Compilers Can be Simple.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis CVC Verilog Compiler -- Fast Complex Language Compilers Can be Simple

Reference 20

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:39.449032Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 12833072-8346-4bfe-8722-0d78e650c9da · outbound

This paper cites Yosys - A Free Verilog Synthesis Suite.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Yosys - A Free Verilog Synthesis Suite

Reference 21

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:39.506913Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation cafe9613-dff3-40b7-9d03-ff31644d2be6 · outbound

This paper cites Openroad: Toward a self-driving, open-source digital layout implementation tool chain,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Openroad: Toward a self-driving, open-source digital layout implementation tool chain,

Reference 22

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:39.596934Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 6c693a86-01d5-427b-af94-a517c17fed44 · outbound

This paper cites Surfer — An Extensible Waveform Viewer,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Surfer — An Extensible Waveform Viewer,

Reference 23

Resolution: verified exact; doi, observed 2026-08-01T22:28:33.564753Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 8303214b-6a3c-41d4-b4a1-dac35fa685d2 · outbound

This paper cites MLIR: Scaling Compiler Infrastructure for Domain Specific Computation,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis MLIR: Scaling Compiler Infrastructure for Domain Specific Computation,

Reference 24

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:39.740716Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 05a80759-5e82-4e71-b16e-2a4029e2823c · outbound

This paper cites Zakharov-Ito equation and Generalized Heisenberg ferromagnet-type equation: equivalence and related geometric curve flows.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Zakharov-Ito equation and Generalized Heisenberg ferromagnet-type equation: equivalence and related geometric curve flows

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:39.829962Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 68a2af08-116e-4554-b3f0-e797fb043f60 · outbound

This paper cites Reusability is FIRRTL ground: Hardware con - struction languages, compiler frameworks, and transformations,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Reusability is FIRRTL ground: Hardware con - struction languages, compiler frameworks, and transformations,

Reference 26

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:39.891598Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 8f42563e-2d0e-46d7-ad12-d0477c1fe81e · outbound

This paper cites LLHD: a multi- level intermediate representation for hardware description languages,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis LLHD: a multi- level intermediate representation for hardware description languages,

Reference 27

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:39.951818Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a834d7c5-0b09-43ca-b299-2d4ea5eee97d · outbound

This paper cites IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process

Reference 28

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:40.022354Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e59257cf-8e41-4027-aa6a-5dc08cda0c06 · outbound

This paper cites AMASIVE: An Adapt - able and Modular Autonomous Side-Channel Vulnerability Evaluation Framework,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis AMASIVE: An Adapt - able and Modular Autonomous Side-Channel Vulnerability Evaluation Framework,

Reference 29

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:40.089031Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 298a929a-1dfe-4a41-980f-8be6d62adaf3 · outbound

This paper cites RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level,

Reference 30

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:40.199252Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b680b4c6-6b01-4741-8d7f-42b405a0d0f0 · outbound

This paper cites SoK: Design Tools for Side-Channel-Aware Implementations,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis SoK: Design Tools for Side-Channel-Aware Implementations,

Reference 31

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:40.248195Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 0ee1d85f-3a58-4008-996f-fc9b199727d1 · outbound

This paper cites YosysHQ/picorv32.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis YosysHQ/picorv32

Reference 32

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:40.309442Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation fedc8ab7-d5fc-4525-bf45-d688f7a50b47 · outbound

This paper cites A Very Compact.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis A Very Compact

Reference 33

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:40.387267Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 8e8db135-b3cd-4bb3-99fa-b4db5a3b839a · outbound

This paper cites Cryptographic IP cores.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Cryptographic IP cores

Reference 34

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:40.463438Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 854d8249-694d-4126-b718-7be178257581 · outbound

This paper cites FORTIFY: Analytical Pre- Silicon Side-Channel Characterization of Digital Designs,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis FORTIFY: Analytical Pre- Silicon Side-Channel Characterization of Digital Designs,

Reference 35

Resolution: unresolved; no resolver link, observed 2026-08-01T22:23:40.533407Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 97b82145-38e1-4604-9778-a583d6f8c29d · outbound

This paper cites Mutual Information Analysis: a Comprehensive Study,.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Mutual Information Analysis: a Comprehensive Study,

Reference 36

Resolution: verified exact; doi, observed 2026-08-01T22:28:33.159786Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 5f80cceb-b542-4577-a2b6-bf8ff1a4bca5 · outbound

This paper cites an unresolved cited work.

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis Unresolved cited work

Reference 165

Resolution: verified exact; doi, observed 2026-08-01T22:28:33.303137Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Pith citing papers

No inbound Pith citation observations are available.