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REVIEW 3 major objections 5 minor 37 references

Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis

T0 review · 3 major / 5 minor · reviewed 2026-08-01 · deepseek-v4-flash

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Pith's one-line read Vogls is a Verilog simulator that combines compiled-code speed, full-timing semantics, and forkable simulation state for pre-silicon side-channel analysis.

desk verdict Vogls is a practical tool paper with a real contribution, but the full-timing fidelity claim needs differential testing and the artifact must be released. read the letter →

arxiv 2607.15782 v1 pith:LAGGLLN6 submitted 2026-07-17 cs.CR cs.AR

Gijs Burghoorn , Ileana Buhan , Lejla Batina This is my paper · ORCID
classification cs.CRcs.AR
keywords pre-siliconside-channelanalysisfull-timingsimulationVerilogsimulatorstateforkingdifferentialpowergate-leveltimingVoglsIntermediateRepresentationtracecollection
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper argues that pre-silicon power side-channel analysis needs a simulator that is fast enough to collect thousands of traces, accurate enough to model gate-level timing including glitches and delays, and controllable enough to fork, mutate, and resume around a point of interest. It presents Vogls, which compiles Verilog designs to C, supports full-timing semantics via specify blocks and SDF annotations, and separates design from state so that a simulation can be copied inexpensively. In benchmarks, Vogls simulates a timing-annotated gate-level AES design 5.9 times faster than the open-source reference simulator Icarus Verilog and runs a PicoRV32 RTL design only 30% slower than Verilator. A case study demonstrates a differential power analysis attack recovering an AES key at RTL, gate-level, and full-timing gate-level abstractions. The pith is that combining these three properties removes a practical barrier: timing-accurate side-channel evaluation no longer forces analysts to restart from reset for every trace.

What carries the argument

The load-bearing mechanism is the Vogls Intermediate Representation (VIR), a temporally-aware SSA/control-flow-graph representation that keeps Verilog's scheduling semantics explicit. VIR lowers to either a bytecode interpreter or generated C code, which the host compiler turns into native code. Around VIR, the design is separated from the mutable simulation state (time, signal values, listeners, update times); forking copies only the state. Timing annotations such as specify blocks and SDF delays are compiled into VIR processes using 'last update time' instructions and timed waits, which is how full-timing glitch behavior is preserved. This combination lets Vogls re-run only a short window

What would settle it

Take a timing-annotated gate-level netlist, simulate the same input vector in Vogls and in a mature full-timing reference simulator (or measure a fabricated FPGA/ASIC implementation), and compare per-transition signal activity and glitch behavior at each timestamp. A divergence in glitch count or transition timing in Vogls relative to the reference would invalidate the claim that Vogls preserves full-timing leakage characteristics and would make the reported minimum-trace-to-disclosure numbers an artifact of Vogls' model rather than a property of the design.

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Extended reading notes

Core claim

The central claim is that a simulator purpose-built for side-channel analysis can simultaneously deliver compiled-code performance, full-timing (sub-cycle) simulation, and fine-grained control over simulation state, and that this combination changes what is practical in pre-silicon SCA. Vogls achieves this by compiling the design to C while retaining a temporally-aware intermediate representation (VIR) that models Verilog scheduling, specify blocks, and SDF timing annotations. State is separated from design, so a simulation can be forked after expensive setup logic and reused across many traces with mutated inputs, preserving the design's timing and leakage characteristics. The paper reports

Load-bearing premise

The load-bearing premise is that Vogls correctly implements IEEE Verilog full-timing delay scheduling (specify blocks and SDF); the paper reports no differential testing against a reference simulator or against hardware to verify this.

Editorial extensions

If this is right

  • Full-timing gate-level SCA trace collection becomes practical on designs previously too slow to simulate; the paper captures 30,000 full-timing traces in about 100 seconds using 8 worker threads.
  • The same DPA workflow runs across RTL, GTL, and full-timing GTL abstraction levels without redesign, enabling direct cross-abstraction leakage comparisons on one design.
  • Adaptive and online side-channel attacks, which need to inspect and mutate simulation state mid-run, are directly supported through the Python interface.
  • VIR provides a unified intermediate representation that could be reused by other tools needing temporal semantics, such as formal timing-property verification or independent pre-silicon SCA analyzers.
  • Because the design is never modified, forking preserves the timing and leakage characteristics of the original circuit for each reused trace.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If Vogls' full-timing semantics prove faithful to real hardware, pre-silicon leakage assessment could routinely catch glitch-based leakages that cycle-accurate simulation misses, shifting countermeasure evaluation toward full-timing by default.
  • The state-forking model implies a natural parallelization strategy: independent state copies need no synchronization, so trace generation can scale across cores or distributed systems without the usual overhead.
  • The 30% performance gap to Verilator is measured on RTL; with the VIR optimizations the paper proposes, compiled Vogls may close much of that gap while retaining full-timing fidelity, making it viable for functional verification as well.
  • A key unresolved question is whether Vogls' timing-accurate glitch behavior on a specific cell library correlates with physical measurements; if it does, Vogls could become a low-cost substitute for FPGA-based leakage assessment in early design iterations.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper presents Vogls, a new open-source Verilog simulator aimed at pre-silicon power side-channel analysis. Vogls compiles Verilog designs to a custom intermediate representation (VIR) and then to either bytecode or native C code. Its main claimed contributions are (1) full-timing simulation performance superior to Icarus Verilog and comparable to Verilator on an RTL design, (2) a Python interface that supports forking, inspecting, and mutating simulation state without modifying the design, and (3) a case study showing a DPA attack recovering an AES key at RTL, GTL, and full-timing GTL abstraction levels. The performance numbers in Table II largely recompute as stated, and the case study in Table III demonstrates the workflow. However, the paper's central full-timing claim rests on an unvalidated delay scheduler, and the discussion in §V explicitly concedes that the test suite mostly stems from bugs found during development.

Significance. If the full-timing semantics are correct, Vogls would fill a genuine gap: no open-source simulator combines compiled-code speed, four-value/full-timing simulation, and interactive state forking. The forking workflow is a meaningful contribution for SCA trace collection, and the case study makes the utility concrete. The paper also provides reproducible benchmark-style measurements and a clear description of VIR. The main risk is that the full-timing model — the key differentiator over Verilator — is not validated against a reference simulator or hardware, so the full-timing MTD value and the 'more accurate timing model' claim are not yet established.

major comments (3)
  1. [§V, §III.B] The load-bearing claim that Vogls provides a 'more accurate timing model' and valid full-timing leakage results is not supported by any differential validation. §V states that the test suite 'mostly stem[s] from bugs found during development,' and no comparison against Icarus Verilog, another IEEE-1364/SDF-compliant simulator, or hardware measurements is reported. The description of lupdt/varwait in §III.B does not establish correct handling of inertial delay/pulse rejection, min:typ:max SDF selection, or timing checks. Since the full-timing MTD of 18,341 traces in Table III and the claim that glitches are modeled depend entirely on this scheduler, the authors should add differential tests against a reference simulator (e.g., Icarus) on the same ICE40 netlist and, ideally, a hardware measurement. Without this, the full-timing column of Table III may be an artifact of Vogls' timing model.
  2. [§IV.A, Table II] The headline performance comparison is stated in a way that is misleading about end-to-end cost. The '5.9x faster than Icarus Verilog' figure compares only simulation time (76.164 s vs 12.798 s) and excludes Vogls' compilation time of 93.167 s versus Icarus' 0.417 s. For a single run, Vogls is not faster; the claim is only valid when compilation is amortized over many traces. The paper should state this amortization explicitly. Additionally, 'only 30% slower than Verilator' is an overstatement: 1.799 s vs 1.441 s is 24.8% slower. Please correct the percentage and discuss the amortization caveat.
  3. [§IV.B, forking workflow] The claim that forking 'preserv[es] timing and leakage characteristics' (Abstract and §III.C) is not empirically demonstrated. The argument that the design is read-only and the entire state is copied is plausible, but a concrete equivalence check — e.g., that a forked simulation produces bit-identical signal traces to a non-forked simulation — would be straightforward and should be reported. This is particularly important because the forked workflow is one of the three headline contributions and is used for all MTD measurements in Table III.
minor comments (5)
  1. [§IV.B, Table III] MTD (Minimum Traces to Disclosure) is used without a formal definition. Define it precisely (e.g., the smallest trace count at which all 16 key bytes are ranked first) and state the attack parameters (number of key hypotheses, ranking criterion, etc.) for reproducibility.
  2. [§III.B] The text says 'a specification is available for VIR' but no URL or reference is given. Please provide a stable link or citation.
  3. [§V] The paper says the source-code repository includes a full overview of supported Verilog concepts, but no repository URL appears anywhere in the manuscript. Since the paper promises open-sourcing 'upon acceptance,' include the URL now or state clearly that it will be added.
  4. [§IV.A] The benchmark environment is described, but not the exact versions of Verilator and Icarus Verilog, nor the C compiler flags used for Vogls' native code path. State versions and flags for reproducibility.
  5. [Abstract] The phrase 'first simulator to combine...' is a strong novelty claim. It would help to cite the specific features in Table I and explicitly contrast with CVC, which is listed as efficient and versatile but not interactive. The current text does not make clear whether CVC's interactive limitations are architectural or simply unverified.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: Vogls' performance and MTD claims are externally benchmarked measurements; self-citations are background only.

full rationale

The paper's central claims are empirical and self-contained against external benchmarks. Table II compares measured compile/simulate times against Verilator and Icarus Verilog on fixed workloads, and Table III reports MTD values from a DPA attack using fixed parameters (fixed target key, random plaintexts, Hamming Distance model). No parameter is fitted to produce the claimed performance ratios or attack results, and there is no equation in which one predicted quantity is defined in terms of another. The strongest caveat—that Vogls' full-timing scheduler is not differentially validated against a reference simulator—is explicitly acknowledged in Section V: 'these tests mostly stem from bugs found during development.' That is a correctness/validation gap, not a circular derivation: an incorrect scheduler could make the MTD numbers empirically wrong, but the results are not true by construction. The self-citations ([19], [31], [33], [36]) support adaptive-attack motivation, a survey, a benchmark S-box design, and a future-work metric, respectively; none is load-bearing for Vogls' performance or attack conclusions. No self-definitional, fitted-input-as-prediction, or uniqueness-imported-from-authors pattern is present.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

Light ledger: this is a measurement/tool paper, so the central claims are benchmark timings and a DPA demonstration rather than derived predictions. No numerical parameter is fitted to data — compile/simulation times are measured, MTD values are measured attack outcomes, and no constant is adjusted to produce the results. Vogls introduces VIR, but that is a software intermediate representation with falsifiable handles (the promised open-source code, the test suite), not a physical postulate in the graviton class. The epistemic load sits on the four domain assumptions listed.

assumptions (4)
  • domain assumption IEEE 1364 Verilog scheduling semantics (event regions, delays, pre-emption) are the correct reference model for full-timing simulation leakage.
    Invoked throughout §III.B: VIR is claimed to follow 'Verilog scheduling semantics,' and the SCA value proposition rests on glitch fidelity (Mangard et al. [15]). If real chips deviate from these semantics, or Vogls deviates from them, the leakage conclusions change.
  • domain assumption The Hamming Distance power model applied to traced signal activity approximates the physical power leakage relevant to a real AES DPA attack.
    Used in §IV.B to derive traces and compute MTD; standard in SCA literature but an acknowledged abstraction — no electrical or technology power model is used.
  • domain assumption SDF/delay annotations from the ICE40 cell library give faithful full-timing data for the gate-level designs.
    Experiment (3) in §IV.A and the GTL/full-timing GTL simulations in §IV.B rely on Yosys-synthesized ICE40 netlists with timing annotations; errors in library timing would propagate directly into the MTD results.
  • domain assumption The Table I survey is complete: no existing simulator combines the three criteria.
    §II.B states 'To our knowledge, no existing Verilog simulator combines (1) efficient, (2) interactive, and (3) versatile.' The survey excludes commercial simulators on license grounds, not capability grounds, so the Abstract's 'first simulator' framing is stronger than the survey supports.

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Cite this review

Pith. "Pith review of Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis." pith.science (2026). https://pith.science/paper/LAGGLLN6

@misc{pith2026260715782,
  author       = {Pith},
  title        = {Pith review of: Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/LAGGLLN6}},
  note         = {Machine review of arXiv:2607.15782}
}
read the original abstract

Designing hardware circuits resistant to side-channel attacks increasingly relies on simulation to predict device leakage before fabrication. Current functional verification simulators are designed for extended correctness-checking runs and are ill-suited for producing large numbers of short trace collections with slight input variants needed for side-channel analysis. We present Vogls: an open-source Verilog simulator built for side-channel analysis, that is the first simulator to combine compiled-code performance, full-timing simulation, and fine-grained control over the simulation state. Vogls simulates a timing annotated gate-level AES design 5.9 times faster than Icarus Verilog and is only 30% slower than Verilator on a PicoRV32 RTL design while also offering a more accurate timing model. Vogls provides a Python interface that allows simulations to be paused, forked, inspected, and mutated around points-of-interest without modifying the hardware design and thereby preserving timing and leakage characteristics. Furthermore, a trace-collection workflow runs setup code once and forks at the point-of-interest, eliminating the need to re-simulate from reset for every trace. A case study demonstrates Vogls on a differential power analysis attack that successfully recovers the key at RTL, GTL and full-timing GTL abstraction levels.

Figures

Figures reproduced from arXiv: 2607.15782 by the authors.

Figure 1
Figure 1. A block diagram of Vogls taking Verilog to bytecode or native code. [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Key-byte rank of the slowest-converging byte versus number of traces [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗

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