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REVIEW 3 major objections 7 minor 36 references

CONQuER shifts mixed-precision quantisation into the compiler and finds hardware-specific policies up to 12.19x faster inference, with top-1 accuracy within 1.44% of the unquantised baseline.

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2026-08-01 01:11 UTC pith:AQCPN3EV

load-bearing objection The TOSA-level integration is a genuine step forward, but the claimed 1,440-inference HIL budget contradicts the 512-image-per-candidate protocol, and the headline numbers are uninterpretable until that is resolved. the 3 major comments →

arxiv 2607.25884 v1 pith:AQCPN3EV submitted 2026-07-28 cs.SE

CONQuER: Hardware-Aware Mixed-Precision Quantisation with Online-Calibrated Surrogates

Aidan Dakhama (1) , Ajitha Rajan (1) ((1) University of Edinburgh) This is my paper
classification cs.SE
keywords mixed-precision quantisationhardware-aware optimisationcompiler-integrated deploymentMLIR/TOSANSGA-IIsurrogate-guided searchhardware-in-the-loop calibrationPareto-optimal neural network deployment
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper's central claim is that the quality of a mixed-precision quantisation policy cannot be separated from the compiler pipeline and physical hardware that will execute it. It argues that current workflows, which quantise models in a hardware-agnostic front-end step, produce policies that map poorly to heterogeneous execution blocks and can even fail to compile. To fix this, it proposes CONQuER, a compiler-integrated infrastructure that generates and evaluates quantised graphs directly in the MLIR TOSA intermediate representation. A dual-surrogate filter prunes the exponential search space before expensive hardware-in-the-loop evaluation, and an online calibrator keeps the surrogates honest. If the central claim is right, developers should expect optimal bit-width assignments to be hardware-specific, and deployment toolchains should treat quantisation as a compiler optimisation rather than a preprocessing step.

Core claim

The paper claims that mixed-precision quantisation is best done inside the compiler's middle-end, at the MLIR TOSA level, rather than as an external preprocessing step. It introduces CONQuER, which generates candidate quantised graphs natively in the IR, uses a dual-surrogate pre-screening engine — a roofline-based hardware cost model plus an information-theoretic accuracy proxy based on the Shannon entropy of activation-covariance eigenvalues — to discard weak configurations cheaply, and then compiles and executes only the most promising candidates on the target hardware via IREE. An online logarithmic calibrator continuously realigns the surrogates with measured hardware behaviour during a

What carries the argument

Dual-surrogate pre-screening engine: a lightweight two-part filter combining a roofline model of node latency (compute vs memory bounds plus dispatch overhead) with an information-theoretic accuracy fragility metric (normalised Shannon entropy of activation-covariance eigenvalues, weighted by 2^{-b} quantisation noise). It prunes the combinatorial space before any physical compilation; the NSGA-II evolutionary search then evaluates only the strongest candidates on hardware, and an online logarithmic calibrator aligns the surrogates with observed latency and accuracy across generations.

Load-bearing premise

The accuracy surrogate assumes that the Shannon entropy of activation-covariance eigenvalues, weighted by 2^{-b} quantisation noise, is an additive per-layer predictor of final top-1 accuracy, and the paper does not validate this predictor against the reported models.

What would settle it

A direct experiment that uses the accuracy surrogate alone to rank candidate mixed-precision policies, then measures their true top-1 accuracy on a held-out validation set, would settle it: if the surrogate's predicted ordering disagrees with the measured ordering on any of the benchmark models, the pre-screening can silently discard the best configurations.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • If CONQuER's claims hold, mixed-precision policies should be tuned per deployment target; the paper reports that transferring a policy across targets misses the native optimum and adds measurable latency penalties in every tested case.
  • Compiler-integrated search prevents the silent deployment failures observed when externally quantised models cannot be lowered by the backend.
  • A strictly capped hardware evaluation budget (1,440 inferences) is sufficient to find strong Pareto-optimal policies when guided by dual surrogates.
  • On compute-proportional hardware, substantial speedups (up to 12.19x) are achievable with accuracy loss below 1.5%; on laptops with FP16 unpacking penalties, the search limits regression but cannot beat FP32.
  • Single-objective surrogates skew the Pareto front; the dual-surrogate configuration produces more stable, higher hypervolume convergence.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • A natural extension is to validate the accuracy surrogate as a standalone, no-training sensitivity score: if its predicted per-layer ordering matches measured accuracy drops, it could be reused outside CONQuER (e.g., in other search loops or as a diagnostic).
  • The online calibrator's logarithmic form could be evolved into a learned backend cost model that amortises calibration across many models compiled for the same target.
  • For dispatch-bound targets like large GPUs running small models, the paper's own data suggests that an early 'compute-proportionality' check could save search budget by falling back to uniform precision or other optimisations.
  • The same compiler-integrated search could be extended to other precision-related compiler decisions, such as operator tiling and vectorisation, turning mixed-precision quantisation into one axis of a broader co-optimisation problem.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 7 minor

Summary. The paper presents CONQuER, a compiler-integrated mixed-precision quantisation (MPQ) infrastructure. Quantisation is performed natively at the MLIR TOSA level; an NSGA-II evolutionary search generates candidate policies, a dual-surrogate pre-screening engine (a roofline-style hardware model and an entropy/isotropy-based accuracy model) filters candidates, and the most promising candidates are compiled and executed on physical hardware via IREE. An online logarithmic calibrator is used to align the surrogates with measured hardware behaviour. The paper reports speedups over an unquantised MLIR FP32 baseline across a Snapdragon 8 Elite, an Intel i5-1145G7, and an NVIDIA A100, with a headline result of 12.19x faster ResNet-50 inference on the A100 at a 1.44% top-1 accuracy drop. It also reports cross-target transfer penalties, ablations of the surrogate components, and comparisons against SeQTO and InfoQ.

Significance. If the experimental claims hold, the paper makes a useful contribution: moving MPQ search into the compiler IR and coupling it to physical execution is a sensible way to avoid the front-end/framework fragmentation that often makes quantised models unsupported or slow after lowering. The final Pareto points are measured directly on hardware rather than predicted by the surrogate, which limits circularity; the cross-target transfer experiments and the surrogate ablation are valuable evidence. The paper also provides a source-code link and repeats runs with five seeds. However, the reported hardware-in-the-loop budget is internally inconsistent, and the comparison against InfoQ is confounded by different runtime stacks. These issues currently prevent verification of the central claim and require a major revision before the results can be accepted.

major comments (3)
  1. [§II.C/§III.A] The hardware-in-the-loop accounting is self-contradictory. §II.C states that each HIL-evaluated candidate measures accuracy on a distinct 512-image split, in addition to 3 warm-up and 10 timed latency runs. §III.A then states that the physical evaluation budget for both SeQTO and CONQuER was 'strictly capped at a maximum of 1,440 hardware inferences.' If 'hardware inference' means one image processed by the model, the entire CONQuER run can HIL-evaluate at most floor(1440/512)=2 accuracy candidates, which cannot produce the converged Pareto fronts in Table IV, the generational trajectories in Figure 3, or the reported 12.19x result. If 'hardware inference' instead means one candidate-policy evaluation, the cap is not comparable to SeQTO's per-image profiling and the term is misleading. The paper never reports population size, number of generations, or the number of HIL-evaluated candidat
  2. [§III.A/Table II] The InfoQ comparison is not apples-to-apples. §III.A says InfoQ's execution latency is evaluated natively using the PyTorch runtime rather than the compiled IREE stack, while CONQuER is compiled and executed via IREE. The large speedup differences in Table II could therefore be due to the runtime/compiler stack rather than to the quantisation allocation method. This confound is especially important for the claim that InfoQ 'universally fails to achieve an absolute speedup.' Please measure InfoQ policies on the same IREE pipeline where they lower successfully, or, if that is impossible, report a same-runtime baseline (e.g., CONQuER-generated policies executed in PyTorch) and separate the effect of the search method from the effect of the deployment stack.
  3. [§II.B] The accuracy surrogate is an unvalidated additive model. The paper assumes that total accuracy degradation is the sum of per-node entropy-weighted noise terms, where the entropy H of activation-covariance eigenvalues is multiplied by quantisation noise amplitude ≈ 2^{-b}. No evidence is provided that this proxy is predictive of actual top-1 accuracy for the five models evaluated, nor that different layers are independent in their accuracy effects. The ablation in Table IV shows that the dual proxy outperforms unguided search, but it does not test whether the surrogate's ranking agrees with hardware-measured accuracy. Since the search uses the surrogate to discard candidates before HIL evaluation, a mis-calibrated proxy could eliminate the best policies. Please report, at minimum, a correlation or rank-agreement analysis between surrogate scores and measured accuracy for a sample of evalu
minor comments (7)
  1. [Abstract] Typo: 'different of model layers' should be 'different model layers' or 'different combinations of model layers.'
  2. [§II.C] The online calibrator is described only as y = a ln(x) + b with a sliding window. It is unclear which surrogate output x is the input, which measured quantity y is the target, how often the coefficients are updated, and whether the calibrator is applied to the accuracy surrogate, the latency surrogate, or both. Please specify the algorithm precisely; this is a named contribution but is not currently reproducible from the text.
  3. [Table I] In the caption and table header, SeQTO is referenced as '[3]' in the column heading but the bibliography gives SeQTO as reference [6]. Please correct the citation.
  4. [Table II] The InfoQ QAT rows are ambiguous: the column label 'QAT Acc↓' reports positive values such as +0.96%, which the text then describes as accuracy being 'resolved' or higher than the original model. Clarify the sign convention and whether the QAT numbers are measured on the training set or the validation set; as written they appear inconsistent.
  5. [Table II] In the Intel i5 column, the ResNet-50 CONQuER latency is listed as '69.06' without the 'ms' unit. Please add the unit.
  6. [Figure 3] The caption says hypervolumes are 'normalised,' but the y-axis values differ substantially across panels (e.g., MobileNetV2 around 0.02-0.045 vs. ResNet-50 around 0.40-0.48). Clarify what normalisation is used or remove the word 'normalised.'
  7. [§III.A] The hardware target names are inconsistent: 'Intel I5 1145g7' in most places but 'Intel Core i5' in Figure 2 and 'i5' elsewhere. Use a single consistent identifier.

Circularity Check

0 steps flagged

No significant circularity; the reported Pareto fronts are direct hardware measurements, not outputs of the fitted surrogates.

full rationale

The central claim—that CONQuER discovers hardware-specific mixed-precision policies with up to 12.19x speedup and accuracy within 1.44% of baseline—rests on final evaluations executed on physical hardware. Section II.C states that 'the most promising candidates identified by the surrogate engine are fully compiled and executed on the target hardware via IREE, using a distinct 512-image search split. Accuracy is measured directly from these hardware executions,' and Section III.A states that 'final Pareto-optimal configurations are independently tested on the remaining unseen images from the validation set.' Thus the reported accuracy and latency numbers are direct measurements, not predictions produced by the surrogate or the online calibrator. The dual-surrogate pre-screen and the online logarithmic calibrator (y = a ln(x) + b) are search-guidance mechanisms: the calibrator is fitted to a sliding window of hardware observations, but it does not generate the final reported Pareto front. The entropy × 2^-b accuracy surrogate is a heuristic model used to prune candidates; it is not the source of the final measured results, so there is no fitted-input-called-prediction reduction. The comparison to SeQTO involves a shared co-author (Rajan), but SeQTO is an experimentally executed baseline rather than a load-bearing citation; no uniqueness theorem or ansatz is imported from self-citations. The unclear 1,440-hardware-inference budget and the lack of validation for the accuracy surrogate are validity/reproducibility concerns, not circularity.

Axiom & Free-Parameter Ledger

3 free parameters · 5 axioms · 0 invented entities

The central claim rests on domain assumptions about surrogate reliability (roofline latency, entropy-based sensitivity, additive accuracy penalties) and the representativeness of the 512-image selection split. The free parameters are the online calibrator coefficients and unspecified evolutionary hyperparameters. No new physical or conceptual entities are postulated; conquer-opt is a software artifact, and the dual-surrogate/calibrator are algorithmic components.

free parameters (3)
  • online calibrator coefficients a,b = not reported
    y = a ln(x) + b is fit to hardware execution metrics during search to align surrogates (Sec. II.C). The paper never reports the fitted values or sliding-window length.
  • NSGA-II hyperparameters = unspecified
    Population size, generation count, mutation/crossover rates are not given; these directly affect search quality and budget.
  • quantisation noise amplitude scaling for low-dynamic-range formats = unspecified
    Sec. II.B says the 2^{-b} noise is 'proportionally scaled' for formats with lower dynamic range; the scaling factor is not defined.
axioms (5)
  • domain assumption Roofline model with max(compute, memory) + dispatch overhead predicts relative node latency across targets
    Used in the hardware surrogate (Sec. II.B, Fig. 1) to prune candidates before HIL; no validation of the model's accuracy is reported.
  • domain assumption Feature-space isotropy entropy measures per-layer quantisation fragility
    Accuracy surrogate (Sec. II.B) uses Shannon entropy of eigenvalues of activation covariance; borrowed from AZ-NAS but not validated for MPQ here.
  • ad hoc to paper Total accuracy degradation is the sum of per-node entropy-weighted noise terms
    First-order Taylor summation of layer penalties (Sec. II.B); no derivation or empirical validation of additive separability.
  • domain assumption 512-image subset accuracy is a sufficient selection signal
    HIL search uses a 512-image split (Sec. II.C); given ImageNet has 50k validation images, this is a small sample with high variance; no confidence intervals provided.
  • domain assumption IREE execution latency and accuracy are the ground truth for deployment
    All HIL metrics come from IREE after TOSA lowering (Sec. II.C); if IREE's FP32 kernels are poorly optimised, speedups over FP32 are inflated.

pith-pipeline@v1.3.0-alltime-deepseek · 15917 in / 13444 out tokens · 121451 ms · 2026-08-01T01:11:46.379594+00:00 · methodology

0 comments
read the original abstract

Deploying deep neural networks on resource-constrained hardware relies on mixed-precision quantisation (MPQ). current deployment toolchains severely fragment this process. Quantisation typically occurs as a hardware-agnostic preprocessing step in front-end frameworks, disconnected from the downstream compilers that generate the physical machine code. This separation leads to suboptimal configurations where assigned bit-widths map poorly to the target machine's heterogeneous hardware execution blocks such as tensor cores and variable-width vector units, incurring severe runtime execution penalties. Furthermore, evaluating these configurations via exhaustive hardware-in-the-loop (HIL) testing is intractable due to the exponentially large search space. We present CONQuER, a unified compiler-integrated infrastructure for hardware-aware MPQ. CONQuER shifts quantisation into the compiler pipeline at the TOSA level, enabling intelligent configuration handling based on compiler support. To evaluate this combinatorial search space of different of model layers within practical compilation budgets, CONQuER couples an NSGA-II evolutionary algorithm with a dual-surrogate prescreening engine. This engine evaluates theoretical cache memory bounds and feature space isotropy to discard non-viable configurations. CONQuER then executes only the strongest candidate policies on hardware via IREE, feeding the execution metrics into an online calibrator. This calibrator aligns the surrogate models with the true hardware behaviour during an NSGA-II evolutionary search. Evaluation across mobile and laptop CPUs, and server GPUs demonstrates that optimal quantisation policies are hardware-dependent. By coupling quantisation with compiler lowering and physical execution, CONQuER discovers Pareto-optimal configurations up to 12.19x faster inference with top-1 accuracy within 1.44% of the unquantised baseline.

Figures

Figures reproduced from arXiv: 2607.25884 by Aidan Dakhama (1), Ajitha Rajan (1) ((1) University of Edinburgh).

Figure 1
Figure 1. Figure 1: Overview of the hardware latency estimation surrogate. [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Cross-target transferability of mixed-precision policies across NVIDIA A100 80GB, Intel I5 1145g7, and Snapdragon 8 Elite. The y-axis shows the [PITH_FULL_IMAGE:figures/full_fig_p007_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Generational trajectory of the average hypervolumes (normalised) vs. Generation across ablation configurations. Single proxies and unguided searches [PITH_FULL_IMAGE:figures/full_fig_p009_3.png] view at source ↗

discussion (0)

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