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Deltoris: Enabling Real-time VLA Inference in Embodied AI via Bit-level Sparsity and Speculative Inference

T0 review · 4 major / 5 minor · reviewed 2026-08-15 · deepseek-v4-flash

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Pith's one-line read By rewriting each linear layer of a diffusion-based vision-language-action model as a differential update $y_t = y_{t-1} + W \Delta x_t$ and computing only the nonzero bit-level parts of $\Delta x_t$, Deltoris cuts arithmetic by up to…

desk verdict A credible co-design with real engineering, but the 34x speedup rests on an unverified premise: latent activations across control steps staying bit-sparse inside a stochastic diffusion chain. read the letter →

arxiv 2608.04428 v1 pith:64OFD2TH submitted 2026-08-05 cs.AR cs.LG

Zheng Liu , Zeyu Guo , Zihan Liu , Anbang Wu , Han Zhao , Fangxin Liu , Zhezhi He , Yinhe Han
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Jingwen Leng Minyi Guo Yiming Gan Yu Feng
This is my paper · ORCID
classification cs.ARcs.LG
keywords vision-language-actionmodelsdiffusionalgorithm-hardwareco-designbit-levelsparsitytemporalredundancyspeculativeinferenceedgeroboticsacceleratorarchitecture
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to show that diffusion-based vision-language-action (VLA) models, which are normally too slow for real-time robot control at 50–200 Hz, can be run at that speed by exploiting a simple observation: consecutive sensory inputs in a closed control loop are nearly identical. Deltoris replaces the full computation at each control step with a differential update $y_t = y_{t-1} + W \Delta x_t$, where $\Delta x_t$ is the sparse bit-level difference between the current and previous input, and a bit-serial accelerator processes only the active bits. To handle the extra memory traffic this creates, it adds a speculative-inference scheme in which a small model proposes future states and a large model verifies them in a batch, amortizing weight and activation loads. The authors report up to 34.2$\times$ speedup over a mobile GPU and 6.1$\times$ over prior diffusion accelerators with only 0.2% success-rate loss across three VLA models and three datasets. If right, embedded robots could run high-quality diffusion policies at control rates previously reserved for much simpler models.

What carries the argument

The load-bearing mechanism is the temporal-difference identity $y_t = y_{t-1} + W \Delta x_t$ (Eq. 2), which converts a full matrix-vector product into a sparse additive update. Deltoris represents $\Delta x_t$ in sign-magnitude form and executes only the active 1-bit events on 1D systolic bit-serial PE arrays with output-stationary dataflow; the speculative-inference stage then batches multiple speculative frames through the same weights to amortize DRAM traffic that the differential computation would otherwise inflate by 80%. The identity plus the batched-verification scheme together carry the claimed reductions in both compute and data movement.

What would settle it

Record the layer-wise activation tensors of a diffusion-based VLA running in closed loop at 50–200 Hz, with the stochastic re-noise term $\sigma_t n'_t$ active, and compute the fraction of active bits in $\Delta x_t$ for every linear layer. If that fraction is near 50% rather than the >90% needed for the claimed 92.9% operation reduction, the reported speedups would not generalize; a simpler check is to compare end-to-end latency with the re-noise term enabled versus disabled.

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Extended reading notes

Core claim

At the core of Deltoris is the identity $y_t = W x_t = y_{t-1} + W (x_t - x_{t-1})$, which turns every linear projection in a diffusion-based VLA model into a differential update over the previous step's cached output. Because robot observations change little at 50–200 Hz, $\Delta x_t$ is sparse at the bit level, so a bit-serial accelerator that processes only the active 1-bits of the sign-magnitude representation of $\Delta x_t$ can skip over 90% of the arithmetic. The paper further claims that this bit-sparsity makes inference memory-bound rather than compute-bound, and that the proposed speculative inference—where a lightweight draft model proposes several future actions and the accurate large model verifies them in a batch—amortizes off-chip weight and activation traffic across control steps. Together with a 1D systolic bit-serial PE array that eliminates the workload imbalance of prior bit-serial designs, Deltoris claims up to 92.9% operation reduction, 34.2$\times$ speedup over a mobile GPU, 6.1$\times$ over the closest prior accelerator, and average success-rate loss of 0.2% on PAD, Diffusion Policy, and UVA.

Load-bearing premise

The speedup rests on the assumption that the numbers entering the network's layers change so little from one control step to the next that their bit-level difference is sparse; the paper demonstrates this for raw camera pixels, but not for internal activations after nonlinearities and after the stochastic re-noising term in each diffusion step.

Editorial extensions

If this is right

  • If the claimed speedups hold, diffusion-based VLA policies like PAD, Diffusion Policy, and UVA could move from roughly 2 Hz on an edge SoC to the 50–200 Hz control rates required for stable closed-loop manipulation, without retraining or model distillation.
  • The bit-sparsity algorithm is bit-accurate for linear operators, so the only accuracy loss comes from the speculative draft–verify step; this makes the approach usable in safety-sensitive control where approximate inference is not acceptable.
  • Since temporal-aware bit-sparsity and inter-timestep similarity exploit orthogonal redundancies, a system combining both could push operation reduction beyond the 92.9% reported here for multi-step diffusion processes.
  • The 1D systolic PE array design, if validated, removes the workload-imbalance bottleneck that has limited prior bit-serial accelerators, making bit-sparse execution viable at high utilization on other workloads with temporal redundancy.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The paper's evidence for temporal similarity is at the pixel level; a direct layer-wise measurement of activation-difference sparsity on a real robot with the stochastic re-noise term active would show whether the 34.2$\times$ figure transfers beyond the three evaluated models and datasets.
  • The batched-verification idea could extend beyond a single robot: if several policies share weights, the same amortization of weight and activation loads could apply across robots or tasks, not just across frames within one control loop.
  • The graceful degradation seen at 2$\times$ scene acceleration suggests an adaptive policy: dynamically shrink the speculative window or fall back to full computation when motion estimates indicate that temporal similarity is dropping.
  • The draft model uses roughly 1/5 of the denoising steps of the large model; using a single-step distilled draft could enlarge the speculative window and further amortize data loading, at the cost of a lower acceptance rate.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. This paper proposes Deltoris, an algorithm-hardware co-design framework for diffusion-based vision-language-action (VLA) inference. The algorithmic core observes that consecutive control steps in robotic loops are highly similar and rewrites each linear projection as y_t = y_{t-1} + W (x_t - x_{t-1}), so that only the bit-level differences in activations need to be computed. To mitigate the extra off-chip traffic caused by the differential computation, the paper introduces speculative inference, in which a small draft model generates several future control steps that are verified in batch by the full model. Finally, the paper presents a 1D systolic bit-serial PE array with weight sharing and claims up to 34.8x speedup over a mobile GPU and 6.1x over prior accelerators with only 0.2% average success-rate loss on PAD, DP, and UVA.

Significance. If the central temporal-sparsity premise holds, Deltoris would be a strong contribution: the differential update in Eq. (2) is an exact identity rather than an approximate fit, and the hardware evaluation is concrete, using post-layout RTL measurements, power simulation, and a cycle-accurate simulator. The approach also advances the architecture literature by targeting diffusion-based VLA inference rather than LLM or image-diffusion workloads. However, the load-bearing assumption that the tensors entering the linear layers are bit-sparse in their temporal difference is only demonstrated on raw camera pixels, not on the latent activations that Eq. (2) actually consumes. This gap, together with the need to clarify the verification protocol of speculative inference, is the main obstacle to accepting the paper's quantitative claims.

major comments (4)
  1. [Sec. 3, Sec. 4.1, Eq. (2), Fig. 8] The central operation-reduction claim rests on the assumption that Delta x_t entering each linear layer is bit-sparse. The only direct evidence of temporal similarity in Sec. 3 (Fig. 7) is measured on raw PushT pixels, not on the activations consumed by the linear projections in Eq. (2). Fig. 8 reports "bit sparsity" for PAD, DP, and UVA, but the text never states how it was measured, at which layers or tensors, or whether the stochastic sampler in Eq. (1) was used. This is load-bearing: Fig. 17c's 93% operation reduction and the speedup numbers scale with the sparsity of Delta x_t. Moreover, Eq. (1) contains the stochastic re-noising term sigma_t n'_t; if the initial latent or the re-noising noise is drawn independently per control step or per denoising step, the corresponding components of Delta x_t are differences of independent Gaussian draws, which are dense under the sign-magnitude representation used in Sec. 4.1. Please add per-layer activation-difference bit sparsity measurements for the actual inference schedule, including the first denoising step, and report the fraction of linear-layer input elements affected by freshly sampled noise.
  2. [Sec. 5, Fig. 12] The speculative-inference protocol as described verifies future actions using the draft model's predicted observations and states as inputs to the large model. In a closed-loop robot, the action at step t+1 should be a function of the actual observation received after executing the accepted action, not of the simulated observation generated by the draft model. The paper should state explicitly whether the success-rate evaluation in Fig. 16 uses this simulated-observation protocol, and it should provide a comparison against a variant in which the large model is re-run on the true observation before each action is executed. This is needed to distinguish a true verification scheme from a model-based rollout and to support the claim that only 0.2% success rate is lost.
  3. [Sec. 8.1, Fig. 16] The accuracy results are reported without confidence intervals or the number of evaluation episodes. The claim that Deltoris loses only 0.2% accuracy while the small model alone loses more than 7.7% is central to the paper's robustness argument, but with no variance information it is unclear whether 0.2% is within noise, especially given the small number of tasks and datasets. Please report per-task success rates, number of rollouts, standard errors, and the per-task acceptance rate of speculative candidates.
  4. [Sec. 7, Tbl. 2] The fairness of the hardware comparison needs clarification. The text states that the compute throughput of all accelerators is configured to be equivalent to 32x32 8-bit MAC units, but Deltoris is described as 128 PE arrays of 64 PEs at 1 GHz, while the baselines have very different organizations (e.g., 512 inner-product units for Pragmatic and 32x32 BitVert units for BBS). Please specify the exact per-cycle bit-level throughput, MAC count, and buffer partition for each design, and explain how the 2.45 mm2 area of Deltoris was obtained under the same technology assumptions. Otherwise the 6.1x speedup over prior accelerators may partly reflect configuration choices rather than the proposed techniques.
minor comments (5)
  1. [Abstract and Sec. 8.2] The abstract reports "up to 34.2x speedup over mobile GPUs," while Sec. 8.2 lists 34.8x, 46.1x, 24.4x, and 31.5x; the abstract also reports 822.0x energy savings while Fig. 17b lists 850x, 1040x, 746x, and 652x. These numbers should be reconciled.
  2. [Eq. (3)] In Eq. (3), v_{t,b} is called a "zero indicator," but the equation sums only over bits with nonzero v_{t,b}; please rename it an "active-bit indicator" to avoid confusion.
  3. [Fig. 8] Fig. 8 would benefit from a labeled y-axis, legend, and a precise definition of how bit sparsity is aggregated across layers, since the caption alone does not specify whether the numbers are weighted by tensor size or by FLOPs.
  4. [Sec. 7, speculative inference] The statement that the draft model "uses roughly 1/5 of the denoising computation of the original model" should specify the exact number of denoising steps and whether the draft and large models share weights or differ only in step count; this affects the interpretation of the speculative overhead.
  5. [Fig. 16] The rendered text in Fig. 16a appears garbled with numeric character references; please ensure the final figure is readable and the per-task success rates are legible.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: temporal differencing is an exact algebraic identity and the headline speedups are measured in RTL/simulator evaluation, not fitted to match a target.

full rationale

Deltoris's central derivation is Eq. (2), y_t = y_{t-1} + W Δx_t, which is an exact algebraic identity; the differential product is then re-expressed in sign-magnitude bit-serial form in Eq. (3). Neither equation defines its claimed result in terms of itself, and no fitted parameter is relabeled as a prediction. The reported 92.9% operation reduction and 34.2x/6.1x speedups are presented as measured outcomes from RTL synthesis, post-layout simulation, and a cycle-accurate simulator on external benchmarks (Meta-World, PushT, LIBERO), not as consequences of constants chosen to force the headline numbers. Self-citations in the reference list (e.g., Astraea, Lumina, Cicero) are used for related-work context or general technique pointers and are not load-bearing; no uniqueness theorem or ansatz is imported from the authors' prior work to forbid alternatives. The main weaknesses of the paper—that activation-level bit sparsity behind the operation reduction is not fully specified, that the stochastic re-noising term in Eq. (1) could reduce temporal sparsity, and that the speculation threshold/window are tuned on PAD—are empirical validity and generalization risks, not circular reductions. Under the requirement that circularity be demonstrated by a quote and a specific reduction, no such step is present.

Assumptions & free parameters 4 free parameters · 6 assumptions · 0 invented entities

The paper's central contribution rests on standard linear algebra plus a strong empirical premise about temporal similarity in the latent space of diffusion VLAs. The key unmeasured premise is that activation differences stay bit-sparse through nonlinear layers; speculative inference adds tuned hyperparameters (threshold, window, draft step count) that affect the reported speedups. No new physical or model-level entities are postulated.

free parameters (4)
  • speculative acceptance threshold theta_th = 0.01
    Selected from a sensitivity sweep on PAD (Fig. 23); balances speedup and task success rate. This threshold directly controls how many speculative candidates are accepted.
  • speculative window size k = 3
    Selected from a sweep on PAD (Fig. 21); larger windows increase draft overhead and lower acceptance, so the value is tuned rather than derived.
  • draft model denoising-step ratio = 1/5 of original denoising steps
    Chosen as the 'small VLA model'; the draft model has the same architecture and dimensions as the large model and only reduces the number of denoising steps, making its cost nontrivial and its acceptance behavior data-dependent.
  • weight-sharing group size M = 16
    Hardware design choice for amortizing SRAM accesses across PE arrays; no sensitivity analysis is reported, so it is a hand-picked configuration affecting reported energy and performance.
assumptions (6)
  • standard math Linearity of linear projections (W x_t = W x_{t-1} + W Delta_x_t) and exact bit-level accumulation of active bits.
    Equations (2) and (3) in Sec. 4.1; the identity holds for linear operators but not for nonlinear activations or attention scores, which the paper handles separately.
  • domain assumption Consecutive control-step observations and robot states are highly similar in real VLA deployments.
    Motivated by PushT pixel statistics (Fig. 7) and the control-frequency argument in Sec. 3; underlies the claimed 92.9% operation reduction.
  • domain assumption Latent activations in the denoising network inherit temporal similarity and remain bit-sparse after nonlinearities.
    Required by Eq. (2) for every linear layer; never directly measured. This is the paper's weakest load-bearing premise.
  • domain assumption The reverse diffusion input at each control step can be treated as temporally similar.
    Eq. (1) includes a stochastic re-noising term n'_t; the paper does not describe how fresh random samples are carried or shared across control steps.
  • domain assumption A step-reduced draft model (1/5 denoising steps) produces candidate futures that the full model accepts often enough to amortize traffic.
    Sec. 5 and Sec. 7 describe the training-free 'distillation' by reduced timesteps; acceptance rate is not reported directly and the threshold and window are tuned on PAD.
  • domain assumption Diffusion-based VLA inference is compute-bound before applying bit sparsity.
    Roofline analysis on Orin and Thor (Fig. 5) motivates reducing arithmetic before addressing memory traffic; this supports the ordering of the proposed techniques.

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Cite this review

Pith. "Pith review of Deltoris: Enabling Real-time VLA Inference in Embodied AI via Bit-level Sparsity and Speculative Inference." pith.science (2026). https://pith.science/paper/64OFD2TH

@misc{pith2026260804428,
  author       = {Pith},
  title        = {Pith review of: Deltoris: Enabling Real-time VLA Inference in Embodied AI via Bit-level Sparsity and Speculative Inference},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/64OFD2TH}},
  note         = {Machine review of arXiv:2608.04428}
}
abstract

Vision-language-action (VLA) models have emerged as a key component in embodied AI. Among existing approaches, diffusion-based VLA models achieve superior motion quality and generalization. However, diffusion-based VLA models are compute-intensive and must run at high control frequency, e.g., 50-200 Hz. Thus, it imposes strict latency and energy constraints on edge devices. In this work, we present Deltoris, an algorithm-hardware co-design framework for efficient diffusion-based VLA inference. First, we exploit the temporal similarity of consecutive inputs and propose a \textit{temporal-aware bit-sparsity} algorithm that computes only the differences between consecutive inputs, eliminating redundant bit-level operations. To further address the extra off-chip traffic introduced by our algorithm, we propose a \textit{speculative inference} technique, which amortizes data loading across multiple control steps. Lastly, to support these techniques, we co-design a dedicated accelerator with customized 1D systolic bit-serial PE arrays that eliminate PE workload imbalance. Our evaluation shows that Deltoris achieves up to 34.2$\times$ speedup over mobile GPUs and 6.1$\times$ over prior accelerators, while maintaining comparable accuracy.

Figures

Figures reproduced from arXiv: 2608.04428 by the authors.

Figure 1
Figure 1. The inference workflow of a VLA model. The vision [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. End-to-end latency of various VLA models. We com￾pare diffusion-based VLA [12, 20, 26, 36, 53] and autoregres￾sive (AR)-based [44, 88, 91] [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 5
Figure 5. Roofline analysis of diffusion-based VLA mod [PITH_FULL_IMAGE:figures/full_fig_p004_5.png] view at source ↗
Figures from the paper (12 more)
Figure 6
Figure 6. Figure 6: Comparison between conventional bit sparsity and our proposed temporal-aware bit sparsity. Left: conventional bit [PITH_FULL_IMAGE:figures/full_fig_p005_6.png]
Figure 7
Figure 7. Figure 7: Temporal similarity of adjacent frames in the VLA [PITH_FULL_IMAGE:figures/full_fig_p005_7.png]
Figure 9
Figure 9. Figure 9: The execution break￾down of VLA models. Self￾attention does not dominate the execution [PITH_FULL_IMAGE:figures/full_fig_p006_9.png]
Figure 12
Figure 12. Figure 12: Overview of our technique, speculative inference. It first allows a lightweight VLA model to generate a sequence of speculative candidates for future steps. These candidates are then verified together by a more accurate VLA model in a batched manner. Thus, we can amor…
Figure 13
Figure 13. Figure 13: Illustration of batched verification in speculative [PITH_FULL_IMAGE:figures/full_fig_p007_13.png]
Figure 14
Figure 14. Figure 14: Overall architecture of the Deltoris. The design consists of multiple 1D PE arrays, a vector unit, an input activation buffer, a weight buffer, and an accumulation buffer. All three buffers are double-buffered to overlap compute with data communication. The 1D PE arra…
Figure 15
Figure 15. Figure 15: Design of 1D PE array. Here, we show how a [PITH_FULL_IMAGE:figures/full_fig_p009_15.png]
Figure 16
Figure 16. Figure 16: Accuracy comparison between the baseline algorithm [PITH_FULL_IMAGE:figures/full_fig_p010_16.png]
Figure 19
Figure 19. Figure 19: Ablation study of Deltoris. We compare differ￾ent configurations, including Base: baseline hardware with weight-only sparsity; Base+Temp: Baseline hardware with temporal-aware bit sparsity; Base+Temp+Sp: baseline hard￾ware with temporal-aware bit sparsity and speculat…
Figure 20
Figure 20. Figure 20: Ablation study on the off-chip data traffic of differ￾ent hardware variants [PITH_FULL_IMAGE:figures/full_fig_p011_20.png]
Figure 22
Figure 22. Figure 22: The sensitivity of performance and normalized en [PITH_FULL_IMAGE:figures/full_fig_p012_22.png]
Figure 23
Figure 23. Figure 23: The sensitivity of performance and accuracy to speculation threshold, 𝜃𝑡ℎ [PITH_FULL_IMAGE:figures/full_fig_p012_23.png]

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Pith tools

Reviewed August 15, 2026 · model on record in the stance chip above.