Optimizing Binary and Ternary Neural Network Inference on RRAM Crossbars using CIM-Explorer

Florian Idrizi; Jan Moritz Joseph; Jos\'e Cubero-Cascante; Lennart M. Reimann; Niklas Degener; Nils Bosbach; Rainer Leupers; Rebecca Pelke

REVIEW 4 major objections 6 minor 41 references

Optimizing Binary and Ternary Neural Network Inference on RRAM Crossbars using CIM-Explorer

T0 review · 4 major / 6 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read CIM-Explorer is an end-to-end toolkit that compiles binary and ternary neural networks onto RRAM crossbars and uses design-space exploration to select mappings and ADC settings that keep inference accurate under device non-idealities.

desk verdict A genuinely useful integrated compiler/DSE toolkit for BNN/TNN inference on RRAM crossbars, with clean mapping algebra and shipped code; the DSE rankings are credible design guidance, but the variability model needs pinning down before treating the TNN-vs-BNN robustness result as hardware truth. read the letter →

arxiv 2505.14303 v3 pith:5FWWQB7S submitted 2025-05-20 cs.ET cs.LG

Rebecca Pelke , José Cubero-Cascante , Nils Bosbach , Niklas Degener , Florian Idrizi , Lennart M. Reimann , Jan Moritz Joseph , Rainer Leupers This is my paper · ORCID

classification cs.ETcs.LG

keywords RRAMcrossbarscomputing-in-memorybinaryneuralnetworksternarydesignspaceexplorationnetworkcompilerADCquantizationdevicevariability

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

CIM-Explorer is a modular software toolkit that takes a pre-trained binary or ternary neural network and compiles it onto RRAM crossbars, where each memory cell stores only a low- or high-resistance state. The paper's central claim is that the same toolkit can serve the whole design process: it estimates inference accuracy under simulated crossbar non-idealities, compares a range of weight-mapping schemes, selects the mapping and ADC settings that preserve accuracy, and then generates code for a fixed crossbar design. This matters because existing CIM tooling tends to cover only compilation, simulation, or design-space exploration separately and usually assumes 8-bit quantization, whereas BNNs and TNNs are the natural workloads for binary RRAM. The paper uses case studies on CIFAR-10 and CIFAR-100 to show that mapping choice, ADC resolution, clipping factor, and LRS/HRS variability interact strongly, and that some commonly used mappings can be outperformed by differential mappings.

What carries the argument

The load-bearing mechanism is the integer-to-digital-to-analog arithmetic transformation. Inputs and weights in {-1,+1} for BNNs or {-1,0,+1} for TNNs are first expressed through digital crossbar values in {0,1}, using either differential mode (two cells per weight, one for the positive and one for the negative part) or linear-scaling mode (one cell per weight with an offset), and then converted to voltages, conductances, and currents with correction terms for the nonzero HRS current and minimum conductance. The ADC is modeled as a clipped mid-rise quantizer with a clipping factor that separates quantization error from clipping error. Modular functional and crossbar interfaces mean the same compiled calls can run on a fast simulator, a detailed simulator, or real hardware.

What would settle it

Run the same BNN and TNN mappings on a fabricated 1T1R RRAM crossbar (or a calibrated independent simulator) at the paper's ADC resolutions and variability levels, and check whether the predicted accuracy ordering, in particular differential BNN VI above XNOR-style BNN V and differential TNN I above linear-scaling TNN IV/V, survives; if a predicted-weak mapping beats a predicted-strong one, the DSE is not faithful to hardware.

Watch

Extended reading notes

Core claim

On its own terms, the paper's discovery is that BNN/TNN-on-RRAM design can be treated as a single, consistent flow instead of separate tools: a compiler rewrites layers into matrix-vector multiplications of a chosen size, a mapper decomposes each integer weight and input through digital crossbar arithmetic into binary voltages and conductances and corrects for analog offsets, and simulators expose the resulting accuracy. In design-space exploration, CIM-Explorer identifies that the differential mapping BNN VI is the most robust to both ADC clipping and cell variability, while the XNOR-style mapping BNN V is the least robust; for TNNs, differential-weight mappings I-III beat linear-scaling mappings IV-V, and TNNs tolerate LRS variability well but are more sensitive to HRS variability because the zero weight is placed in the HRS. It further finds that larger BNNs trained on the same dataset can be less sensitive to hardware non-idealities than smaller models of comparable baseline accuracy, and that some networks need only a 3-bit ADC to hold accuracy within 1 percent of baseline.

Load-bearing premise

The rankings and accuracy estimates rest on a simplified simulator model in which cell-to-cell and cycle-to-cycle variability are independent Gaussian fluctuations around fixed HRS/LRS current means and the ADC is a clipped mid-rise quantizer; if real RRAM variability is correlated, non-Gaussian, or interleaved with wire resistance and I-V nonlinearity, the recommended mappings may not be the best on actual hardware.

Editorial extensions

If this is right

A designer can, before fabrication, choose a mapping and ADC resolution for a given BNN/TNN and crossbar size, since the DSE outputs accuracy as a function of these parameters.
Mappings that look attractive in the literature need not win on hardware: the XNOR-style BNN V mapping is dominated by differential BNN I/II/VI, so accuracy-aware design-space exploration can retire it.
For TNNs, differential weight mappings should be preferred when cell budget allows; linear-scaling mappings are cheaper but less robust, and TNNs should expect HRS variability to hurt more than LRS variability.
Larger binary networks can be a safer choice under device non-idealities than smaller ones with comparable clean accuracy, since the tolerated ADC resolution and variability are higher.
Because the DSE and the final code generation use the same compiler and mapping path, the accuracy estimated during exploration is consistent with what a finalized crossbar chip would execute.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

If the simulator is validated against measured RRAM arrays, the mapping rankings (BNN VI over I/II over III/IV over V, differential TNN I over II/III over IV/V) could become design rules for RRAM CIM macro specifications before any circuit-level simulation.
The 2-bit bit-sliced encoding used for TNNs suggests a natural route to higher-precision networks: apply the same digital-crossbar decomposition to 4-bit or 8-bit values, at the cost of more cells or cycles.
The ADC clipping factor could itself be tuned per layer or per mapping rather than globally, which would expose accuracy-versus-energy tradeoffs beyond those reported.
The modular functional interface means the same compiled BNN/TNN binary could target an emulator, a simulator, and a real chip unchanged, making lab measurements directly comparable to the paper's accuracy estimates.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

First thing to know: CIM-Explorer is a real engineering contribution, not just another DSE wrapper. It couples a TVM-based compiler with a Larq frontend, multi-batch write reuse, several BNN/TNN mappings, and a DSE flow that runs through the same compiler, so the execution order used in DSE matches code generation. The mapping algebra in Section 4.2 is internally consistent; I checked the correction terms for BNN I and III and they work. The code is on GitHub. As far as I can tell from the related work, the integrated BNN/TNN-specific flow is new.

That is the main point. The modular interface design is sensible and the paper is clearly written. The DSE sweeps alpha, ADC resolution, and cell variability; they do not fit parameters to produce conclusions, so the circularity burden is low. Credit is due: the authors explicitly note that the strong HRS-variability effect is partly a modeling artifact of the asymmetric Gaussian.

Where it is soft: the validation is simulation-only. The ADC model is a mid-rise quantizer with a clipping factor, and cell currents are independent Gaussians. The stress-test about truncation is fair: the text says negative currents are impossible and the HRS distribution becomes asymmetric, but it never specifies whether negative samples are clipped, re-sampled, or discarded. That matters because TNNs store the zero weight predominantly in HRS, so any truncation that shifts the HRS mean upward as sigma_hrs grows will disproportionately hurt TNNs. The "TNNs are less robust to HRS variability" ranking in Figures 7/9 could be partly manufactured by this modeling choice. This does not sink the paper—they already acknowledge the asymmetry—but the ranking should be re-tested with a physically grounded distribution (lognormal or measured data) and the exact truncation procedure should be documented. Minor: the main figures lack baseline accuracy markers and error bars, which makes the small differences hard to interpret.

Bottom line: for tool builders and anyone doing early RRAM crossbar DSE for BNN/TNN inference, this is a useful, citable piece. The quantitative robustness rankings are design guidance, not hardware predictions. I would send it to peer review; it deserves referee time.

Referee Report

4 major / 6 minor

Summary. This manuscript presents CIM-Explorer, an open-source toolkit that compiles binary and ternary neural networks to RRAM crossbar-based CIM accelerators, simulates their inference under non-idealities, and performs design-space exploration. The paper's main contributions are a TVM-based compiler with a Larq frontend, six BNN and five TNN integer-to-analog mappings with explicit correction terms, a modular functional/crossbar interface, and a DSE flow that sweeps ADC clipping/resolution and LRS/HRS current variability. Case studies on CIFAR-10 (VGG-7) and CIFAR-100 (BinaryNet, BinaryDenseNet28/37) lead to conclusions such as BNN VI being the most robust mapping, TNNs being less robust to HRS variability, and larger BNNs tolerating more variability.

Significance. If the reported DSE results are reproducible and the underlying device/ADC models are representative, the toolkit would be a useful contribution: it is one of the few open-source end-to-end flows for BNN/TNN-on-RRAM that couples compilation and accuracy estimation, and the modular interfaces are designed to accept other simulators or real hardware. The mapping algebra with explicit digital and analog correction terms is a valuable reference, and the availability of the code on GitHub is a concrete strength. However, the quantitative DSE conclusions are not yet convincing: the stochastic cell-current model is underspecified at the truncation of negative currents, baselines are missing from the main accuracy figures, and there is no validation against measured data or an independent simulator. The significance of the central claim is therefore conditional on those points being addressed.

major comments (4)

[Section 5, 'LRS and HRS Variability'] The cell-variability model is underspecified in a way that directly affects the paper's main DSE ranking. The text states that currents are drawn from normal distributions with means µ_L = I_lrs and µ_H = I_hrs and standard deviations σ_lrs/σ_hrs, and later acknowledges that 'negative currents are not possible' and that the distribution around I_hrs is asymmetric, but it never states how negative samples are handled (truncated, clipped, re-sampled, or replaced). Any of these procedures raises the effective mean of the HRS population as σ_hrs grows. Since TNNs map the zero weight predominantly to HRS, this upward shift disproportionately degrades TNN accuracy and may manufacture the observed 'TNNs are less robust against HRS variability' conclusion in Fig. 9. Please specify the exact sampling procedure, justify it against measured RRAM variability data or a standard device model, and re-run the HRS-variability experiments with a distribution that is non-negative by construction (e.g., lognormal) or with an explicitly stated truncation.
[Section 5, Figures 6-9] No baseline accuracy is reported for the CIFAR-10/VGG-7 experiments. The text says 'the original accuracy is maintained' and that accepted parameter ranges keep the 'absolute accuracy drop remains below 1%', but Figures 6-9 show only absolute accuracy values without a baseline line or number; only Table 4, for CIFAR-100, lists baseline accuracies. Without the noiseless or ideal-ADC baseline, the reader cannot verify these claims or compare mappings. Please add the baseline accuracy to each plot and state the baseline for every DSE experiment.
[Section 4.2, Eq. (4)] The ADC model in Eq. (4) is defined for a single differential column current with maximum magnitude i_max = N(I_lrs - I_hrs). It is not explained how this model is applied to mappings with multiple differential terms or to linear-scaling mappings. For example, BNN VI and TNN I combine four crossbar terms (Tables 2 and 3), and TNN IV/V use linear scaling with a non-zero offset; the input range presented to the ADC, and hence the clipping factor α, may differ per mapping and per cycle. Please state explicitly how Eq. (4) is instantiated for each mapping in Tables 2 and 3, including the per-MVM range and any offset, and verify that the same α has the same meaning across all mapping comparisons in Figures 6 and 8.
[Section 5 and Section 6] The quantitative DSE results are produced entirely by the authors' own simulator, with no comparison to measured RRAM arrays or to an independent simulator such as CrossSim. Since the central claim is that CIM-Explorer provides 'expected accuracy' that can guide hardware selection, at least one sanity-check experiment is needed—for example, reproducing a published accuracy-vs-variability result or fitting the model to measured I-V data—to show that the simplified ADC and Gaussian-variability models do not steer the mapping rankings. This is a correctness-risk concern, not a demand for exhaustive device calibration.

minor comments (6)

[Section 3.1, Eq. (1)] The definition of the ternary threshold is incomplete: the text says only that '∆ depends on the weights' and cites [15], but does not give the formula or the training configuration used in the experiments. Please provide the exact thresholding rule.
[Section 4.2, mapping formulas] The conversion formulas such as g_D = g_A - G_min/G_mm and i_D = i_A - I_hrs/I_mm are missing parentheses and are ambiguous under standard operator precedence; they should be written as (g_A - G_min)/G_mm and (i_A - I_hrs)/I_mm.
[Tables 1 and 3] The #Cycles and #Cells/weight entries are easy to misread, especially for BNN VI and the TNN rows. Please use explicit alternatives such as '2 cycles/2 cells per weight' or '1 cycle/4 cells per weight' for BNN VI, and add a note that the TNN two-bit inputs/weights require two cells per bit.
[Figures 7 and 9] The subfigure captions are inconsistent with the text: the captions read '(a) µ_hrs = 5 µA' etc., but the text says that (a)/(b) vary σ_lrs and (c)/(d) vary σ_hrs. Please align the captions with the parameter actually swept.
[Table 4] All three CIFAR-100 models report the same maximum HRS sigma of 5 µA. Please state the sweep step size and explain why the threshold is identical for all models, or report finer-grained results.
[Footnote 1] The CIM-Explorer URL is truncated in the footnote ('.../CIM-E'); please give the full URL so the reproducibility claim can be checked.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: CIM-Explorer's DSE results are simulator outputs, not fits or self-referential derivations.

full rationale

The paper's central claim is that CIM-Explorer provides an end-to-end modular flow for compiling BNNs/TNNs to RRAM crossbars and estimating accuracy under non-idealities. This claim is supported by the described compiler, mapping algebra, and simulator implementation. The mapping equations (Tables 1-3, Eq. 2) are exact algebraic rewrites; the digital and analog correction terms are defined so that in the ideal case the expression reduces to the original arithmetic, so no 'prediction' is smuggled in by construction. The DSE results (Figs. 6-9, Table 4) are outputs of the authors' own simulator under explicitly swept parameters (ADC resolution, clipping factor, sigma values), not quantities fit to target conclusions. There is no fitted parameter renamed as a prediction, and no uniqueness theorem or prior-work premise is invoked to force the outcomes. The paper does contain self-citations (e.g., [6] for the 256x256 crossbar size choice and [18-20] for RRAM reliability context), but these are not load-bearing for the central claim; the tool and its results stand on the described implementation and experiments. The paper also explicitly acknowledges that the strong HRS-variability effect partly stems from the asymmetric Gaussian model (negative currents impossible), which is a modeling limitation affecting hardware transferability, not a circular derivation. Overall, no circular step reduces the paper's conclusions to its inputs.

Assumptions & free parameters 5 free parameters · 6 assumptions · 0 invented entities

The DSE results depend on several user-chosen current levels, ADC settings, and variability parameters, plus a simplified hardware model with linear cells and an ideal analog subtraction of differential columns. These are not measured from a specific RRAM process, so the quantitative conclusions are conditional on the model.

free parameters (5)

ADC clipping factor alpha = swept 0.0 to 1.0 (not fitted)
Introduced in Eq. (4) to set the usable fraction of the ADC input range. The main accuracy results are reported as a function of this parameter.
ADC resolution B = 3 to 8 bits (swept)
Swept in Figures 6-9; the paper concludes that 3-4 bits can suffice for some networks based on this sweep.
HRS current mean = 5 uA or 10 uA
Chosen by hand in the experiments; not tied to a specific device datasheet in the paper.
LRS current mean = 10 uA or 30 uA
Chosen by hand; the variability results and tolerance thresholds depend on this choice.
Cell variability standard deviations = up to 8 uA (swept)
Swept to find maximum tolerable sigma; the threshold is defined by the authors as an accuracy drop below 1%.

assumptions (6)

domain assumption ADC output follows the mid-rise uniform quantizer with clipping in Eq. (4).
This simplified ADC model is introduced in Section 4.2 and is used for all accuracy estimates in Section 5.
ad hoc to paper Cell currents are independent Gaussian random variables with means Ilrs/Ihrs and specified standard deviations, truncated to non-negative values.
Section 5 states a normal distribution but gives no truncation rule; the HRS tail would otherwise include negative currents.
domain assumption Differential columns are subtracted in the analog domain before ADC conversion.
Assumed in Eq. (3) and used for all differential mappings in Tables 2 and 3.
domain assumption RRAM cells have only two conductance states with Gmin > 0 and a linear current-voltage relationship, with no wire resistance or IR-drop.
The paper models variability only on cell currents and omits other crossbar non-idealities listed in Section 1.
domain assumption Read voltages are binary and unipolar, Vr in {0, 0.2 V}.
Stated in Section 4.2 as a reason integer MVM cannot be executed directly on the crossbar.
domain assumption Pre-trained Larq networks represent the baseline accuracy that should be reproduced under ideal crossbar conditions.
The accuracy drops in Section 5 are measured relative to this software baseline, which is not shown in Figures 6-9.

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Cite this review

Pith. "Pith review of Optimizing Binary and Ternary Neural Network Inference on RRAM Crossbars using CIM-Explorer." pith.science (2026). https://pith.science/paper/5FWWQB7S

@misc{pith2026250514303,
  author       = {Pith},
  title        = {Pith review of: Optimizing Binary and Ternary Neural Network Inference on RRAM Crossbars using CIM-Explorer},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/5FWWQB7S}},
  note         = {Machine review of arXiv:2505.14303}
}

read the original abstract

Using Resistive Random Access Memory (RRAM) crossbars in Computing-in-Memory (CIM) architectures offers a promising solution to overcome the von Neumann bottleneck. Due to non-idealities like cell variability, RRAM crossbars are often operated in binary mode, utilizing only two states: Low Resistive State (LRS) and High Resistive State (HRS). Binary Neural Networks (BNNs) and Ternary Neural Networks (TNNs) are well-suited for this hardware due to their efficient mapping. Existing software projects for RRAM-based CIM typically focus on only one aspect: compilation, simulation, or Design Space Exploration (DSE). Moreover, they often rely on classical 8 bit quantization. To address these limitations, we introduce CIM-Explorer, a modular toolkit for optimizing BNN and TNN inference on RRAM crossbars. CIM-Explorer includes an end-to-end compiler stack, multiple mapping options, and simulators, enabling a DSE flow for accuracy estimation across different crossbar parameters and mappings. CIM-Explorer can accompany the entire design process, from early accuracy estimation for specific crossbar parameters, to selecting an appropriate mapping, and compiling BNNs and TNNs for a finalized crossbar chip. In DSE case studies, we demonstrate the expected accuracy for various mappings and crossbar parameters. CIM-Explorer can be found on GitHub.

Figures

Figures reproduced from arXiv: 2505.14303 by the authors.

**Figure 2.** The CIM architecture components considered in this work. [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗

**Figure 3.** The interfaces of the toolkit. The functional interface separates compila [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗

Figures from the paper (6 more)

**Figure 4.** Figure 4: The compiler pipeline including pre-trained inputs, a new frontend, par [PITH_FULL_IMAGE:figures/full_fig_p007_4.png]

**Figure 5.** Figure 5: Scheduling primitives are applied to the initial loop nest of Conv2D. [PITH_FULL_IMAGE:figures/full_fig_p008_5.png]

**Figure 6.** Figure 6: Top-1 % classification accuracy for CIFAR-10 trained on VGG-7 for different ADC resolutions and BNN mappings depending on parameter αADC. (a) µhrs = 5 µA (b) µhrs = 10 µA (c) µhrs = 5 µA (d) µhrs = 10 µA [PITH_FULL_IMAGE:figures/full_fig_p012_6.png]

**Figure 7.** Figure 7: BNN accuracy for CIFAR-10 trained on VGG-7 for different LRS/HRS [PITH_FULL_IMAGE:figures/full_fig_p012_7.png]

**Figure 8.** Figure 8: Top-1 % classification accuracy for CIFAR-10 trained on VGG-7 for different ADC resolutions and TNN mappings depending on parameter αADC [PITH_FULL_IMAGE:figures/full_fig_p013_8.png]

**Figure 9.** Figure 9: TNN accuracy for CIFAR-10 trained on VGG-7 for different LRS/HRS [PITH_FULL_IMAGE:figures/full_fig_p014_9.png]

Discussion (0). Continue with ORCID to comment.

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