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REVIEW 5 major objections 6 minor 1 cited by

HAQA: A Hardware-Guided and Fidelity-Aware Strategy for Efficient Qubit Mapping Optimization

T0 review · 5 major / 6 minor · reviewed 2026-08-16 · deepseek-v4-flash

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Pith's one-line read Most quantum circuits never need the whole chip: pruning the coupling graph to a small high-fidelity region makes optimal qubit-mapping solvers up to 632x faster while preserving solution quality.

desk verdict HAQA is a real, useful engineering contribution for solver-based qubit mapping, but its quality guarantee is only verified on the easy circuits, not the hard ones where the speedups are largest. read the letter →

arxiv 2504.16468 v1 pith:5PWPLCVA submitted 2025-04-23 quant-ph cs.ET

Wenjie Sun , Xiaoyu Li , Lianhui Yu , Zhigang Wang , Geng Chen , Desheng Zheng , Guowu Yang This is my paper · ORCID
classification quant-phcs.ET
keywords qubitmappingquantumlayoutsynthesisSAT/SMTsolverscommunitydetectionfidelity-awarecompilationcouplinggraphpruningHellingerfidelitycircuitoptimization
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper proposes HAQA, a pre-processing wrapper for solver-based qubit mapping. It prunes a processor's full coupling graph down to a small, highly connected, high-fidelity region centered on the logical qubits, then hands that region to an existing solver. The claim is that this pruning shrinks the solver's variable and constraint counts from hardware-scale to circuit-scale, producing hundred-fold speedups (up to 632.76x for Qsynth-v2 and 286.87x for TB-OLSQ2) without degrading circuit depth or swap count and with average-to-large gains in Hellinger fidelity. A sympathetic reader would care because solver-based mapping, though optimal, currently times out on large chips; if HAQA works, near-optimal mapping becomes practical on 100+ qubit devices.

What carries the argument

The load-bearing object is the final mapping graph $C_f = (P_f, E_f)$ chosen by two steps: Recursive Community Fusion, an agglomerative merging of coupling-graph nodes scored by $F = Q + \omega E$, where $Q$ is modularity and $E$ is the average two-qubit gate fidelity of the merged community, and Community Expansion, which adds $k$ rings of adjacent physical qubits to supply ancillas for swaps. This graph replaces the whole chip in the solver call. Its role is to convert the solver's complexity dependence on chip size $n_P, n_E$ into a dependence on circuit size $n_q$ and maximum degree $d_{\max}$; equations (26)-(29) express the pruned variable, clause, and constraint counts in terms of qubit and edge pruning ratios, and this substitution is the mechanism behind the claimed polynomial acceleration.

What would settle it

Take a circuit and a device where the only high-fidelity route between two frequently interacting logical qubits runs through qubits outside the $k=1$ expanded community, and lower the reported fidelity of all region edges to force that situation. If HAQA's pruned solver then returns a mapping with strictly more swaps, larger depth, or lower Hellinger fidelity than the unpruned solver would find within the same time budget, the paper's claim that pruning preserves solution quality fails.

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Extended reading notes

Core claim

HAQA's central claim is that global optimal layout synthesis can be replaced by region-guided synthesis without losing solution quality. Recursive community fusion uses a modularity-plus-fidelity reward $F = Q + \omega E$ to build a hierarchy of connected subgraphs; community expansion then adds one ring of neighbor qubits ($k=1$). The resulting final mapping graph has $n_P \le n_q d_{\max} + 1$ qubits in the worst case and $n_P = n_q + 1$ in the best case, so the solver's hardware-dependent terms drop from $O(n_P)$/$O(n_E)$ to polynomial in $n_q$. On 25 benchmark circuits run against two baseline solvers on 127- and 133-qubit devices, the wrapper reports average speedups above 57x and peak speedups of 632.76x and 286.87x, with circuit depth and swap counts essentially unchanged and Hellinger fidelity up 52.69% and 238.28% in the best cases. The paper also gives a transferable complexity framework: substituting the pruned graph's vertex and edge counts into the solvers' variable and clause formulas predicts the polynomial reduction that the runtime data exhibits.

Load-bearing premise

The central assumption is that a small region of the chip around the circuit's logical qubits, the logical count plus one layer of neighboring qubits, always contains enough high-fidelity routing paths that the optimal global solution loses nothing.

Editorial extensions

If this is right

  • Solver-based qubit mapping, previously limited to roughly 50 two-qubit gates before timing out, can be applied to deep circuits on 100+ qubit processors.
  • Fidelity information enters the mapping process without changing the solver's discrete formulation, because region selection does the fidelity work before solving begins.
  • The acceleration is predicted by complexity analysis: variable and clause counts for Qsynth-v2 drop by up to quadratic polynomial order, and for TB-OLSQ2 by linear polynomial order.
  • HAQA is solver-agnostic, so wrapping other SAT or SMT mappers with the same region-pruning procedure should transfer the speedup.
  • Mapping quality is preserved in depth and swap count, so users do not trade optimality for speed.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial: The $k=1$ expansion rule tunes a trade-off that likely depends on circuit structure; circuits whose interaction graph is denser than the device's local community may need a larger ring, and the paper's own Table 5 already hints that $k=2$ can hurt. A testable extension is to set $k$ per circuit from the ratio of logical-graph edges to region edges.
  • Editorial: Because region selection is guided by an average edge-fidelity score, the method's fidelity gains rely on the accuracy of the device's reported two-qubit error rates; if those drift, the chosen region's advantage may shrink. Re-running HAQA with shuffled or outdated fidelity maps would quantify this sensitivity.
  • Editorial: The complexity-transfer argument suggests a broader recipe: any solver-based optimization whose variables scale with the hardware graph can be wrapped by a topology-aware region selector. Applying the same pruning ratios to routing or gate-scheduling problems is a natural next test.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

5 major / 6 minor

Summary. The paper proposes HAQA, a wrapper around solver-based qubit mappers (Qsynth-v2 and TB-OLSQ2) that first identifies a small region of the hardware coupling graph using a community-detection procedure guided by both topology and two-qubit-gate fidelity, then expands the region by one layer of neighboring qubits, and finally runs the baseline solver only on the induced subgraph. The claimed results are large speedups (up to 632.76x for Qsynth-v2 and 286.87x for TB-OLSQ2), improved Hellinger fidelity on average (up to 52.69% and 238.28% respectively), and roughly preserved depth and swap counts. A complexity analysis argues that the number of solver variables and constraints is reduced from quantities depending on the full hardware graph to quantities depending essentially on the logical qubit count.

Significance. If the claims are fully validated, HAQA would be a practically useful and easily adoptable front-end for exact qubit mappers, and the paper has several strengths: the complexity analysis is explicit and grounded in the published variable/constraint counts of the two baselines, the code is made available, and the speedup trend is large and consistent across two modern IBM architectures. However, the current validation is incomplete: quality metrics are reported only on a subset of circuits, no fidelity-agnostic control isolates the effect of the hardware-guided selection, a central fidelity formula appears incorrect, and a key parameter of the method is not reported. These issues must be addressed before the central claims can be considered established.

major comments (5)
  1. [Eq. (1)] The fidelity, depth, and swap evaluation is restricted to circuits solvable by both baselines, which excludes adder_n10_transpiled, barenco_tof_5, mod_mult_55, qft_8, and the vqe_8_*_10_100 circuits. These are precisely the instances whose baseline timeouts produce the largest speedups in Tables 6-7. For these circuits no reference depth, swap count, or fidelity is reported, so the paper's claim that the acceleration is not bought by quality loss is unsupported in the very regime where HAQA is asserted to be most valuable. The reported subset also contains clear per-instance degradations, e.g., Table 10 reports -17.8% fidelity for adder_n10_transpiled and -17.02% for barenco_tof_4, Table 8 reports -1.72% for tof_5, and several rows show increased depth or swap count (barenco_tof_4, vqe_8_3_5_100, vqe_8_4_5_100). The authors should report quality metrics for all circuits on which the baseline terminates, and for the timeout instances they should either run the baselines with a larger timeout or provide a bound on the optimality gap introduced by the region pruning.
  2. [Eq. (1)] The Hellinger fidelity formula is incorrect as written. The standard expression is HF = (1 - (1/2) * sum_i (sqrt(p_op_i) - sqrt(p_on_i))^2)^2, not the expression with (p_op - p_on)^2 that appears in Eq. (1). If Eq. (1) was actually used in the simulations, the reported metric is not Hellinger fidelity; if instead a correct library function was used, the equation should be fixed. Either way, the central fidelity metric must be stated correctly for the results to be reproducible and interpretable.
  3. [Section 4.2, Eq. (6)] The reward function F = Q + ωE introduces a parameter ω, but the text immediately switches to calling it 'the weight parameter w' and never reports the chosen value or a sensitivity analysis. Since Q and E have different scales and the fidelity-aware region selection is a core claimed contribution, omitting this parameter makes the experiments irreproducible and leaves open the possibility that the results depend strongly on an arbitrary choice. Please specify the value used and provide a brief sensitivity study over ω (including ω = 0 as a connectivity-only control).
  4. [Section 6.2 (experimental design)] The experiments compare HAQA-wrapped solvers against global solvers, but this conflates the effect of reducing the graph size with the effect of the hardware-guided, fidelity-aware region selection. To support the claim that the community-based and fidelity-aware selection (rather than merely using a smaller graph) is responsible for the speedup and fidelity gains, the authors should add a control that runs the baseline solver on a same-size region chosen by a topology-only criterion (e.g., ω = 0) or by a random connected subgraph. A comparison with the subgraph-identification method of Guo et al. [26] would also help position the contribution.
  5. [Section 6.1, Table 5] The expansion factor k is tuned on the same benchmark set that is later used for the main evaluation: Table 5 reports eight vqe circuits on IBM Heron, and k = 1 is then adopted for the headline results. This is a form of test-set tuning. The authors should either select k on a separate validation set or demonstrate that the main conclusions are stable across k = 0, 1, 2 for all benchmark circuits and both architectures.
minor comments (6)
  1. [Section 5, Eqs. (18)-(19)] Both equations are labeled with n^b_var,tbolsq2; the second should be n^w_var,tbolsq2 for the worst case.
  2. [Algorithm 2] Algorithm 2 uses the variable S in the expansion loop, but S is not defined in that algorithm; it should likely refer to the current region Pr or the growing set Pf. Also, the loop iterates over the fixed edge set Er, so it is unclear how multi-hop expansion is actually implemented.
  3. [Section 4.2, Eq. (6)] The notation is inconsistent: Eq. (6) uses ω but the surrounding text uses w for the same weight parameter. Please unify the notation.
  4. [Table 4] The definitions of d_min and d^b_min/d^w_min are never used in the analysis; either use them or remove them to avoid confusion.
  5. [Section 2.2] There is a typo in the heading 'Sovler-based qubit mapping'; it should be 'Solver-based qubit mapping'.
  6. [Tables 6-7] The use of '>' in the Acc-Ratio column for timeout baselines should be explained explicitly in the caption; currently the reader has to infer that those entries are lower bounds, while the text later reports exact 'up to' values from non-timeout rows.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity; the speedup derivation follows from algebraic substitution into external solver complexity formulas, and the evaluation caveats are evidence gaps, not circular reductions.

full rationale

The derivation chain is not circular. HAQA's central mechanism is to prune the hardware coupling graph to a region of about nq qubits before invoking the external solvers Qsynth-v2 and TB-OLSQ2; the claimed acceleration is obtained by substituting the region-size bounds of Eqs. (9)-(11) and the pruning ratios of Eqs. (24)-(25) into the baseline complexity formulas of Eqs. (2)-(5), producing Eqs. (26)-(29). This is algebraic variable accounting, not a prediction that is identical to its input: the speedups in Tables 6-7 are measured runtimes, and the reduced variable/constraint counts are derived from explicit nP/nE substitutions. The paper does not rely on self-citations for its load-bearing claims: the baseline solvers are cited from independent groups, the community-detection primitive comes from Newman's classic algorithm, and fidelity is computed from IBM hardware noise data rather than from the solver output. Two evaluation weaknesses are real but are not circularity: (1) the expansion factor k=1 is selected in preliminary experiments on the same benchmark family used for evaluation, which may inflate the apparent gains but does not make any derived quantity equal to a fitted parameter by construction; and (2) Section 6.3 explicitly restricts fidelity/depth/swap comparisons to circuits solvable by both baselines, so solution quality on the timeout instances producing the headline speedups is unverified. That is a missing-evidence or correctness-risk concern, not a definitional or self-citation circularity. Accordingly, the circularity score is 0.

Assumptions & free parameters 2 free parameters · 4 assumptions · 0 invented entities

No new physical entities are introduced. The method's load-bearing components are the reward function and expansion factor, both under-specified or tuned, listed above. All other inputs are standard graph and solver machinery.

free parameters (2)
  • Reward weight omega = not reported
    Eq (6) defines F = Q + omega*E, balancing modularity and average fidelity; no value is given anywhere, so region selection cannot be reproduced or audited.
  • Expansion factor k = 1 (selected via Table 5)
    Chosen by preliminary experiments in Table 5; the same benchmark family is later used in main results, so k is a tuned hyperparameter rather than a derived constant.
assumptions (4)
  • domain assumption The circuit can be mapped inside a small subgraph: nq <= nm <= nP, and a region of roughly nq+k physical qubits is sufficient.
    Section 4.1 states this observation and Section 4.3 motivates expansion; the entire speedup depends on this being true for all benchmark circuits.
  • ad hoc to paper The reward F = Q + omega*E selects regions that preserve solution quality while improving fidelity.
    No theorem or control experiment justifies this particular combination of modularity and average fidelity; it is a design choice validated only by the main experiments.
  • domain assumption Degree statistics of the selected subgraph are similar to the global graph (Eqs 12-13), and a chain-like subgraph is the worst case.
    Used in Section 5 to bound nw_P and nw_E; if the selected community can have higher boundary degree, the complexity reduction may be overestimated.
  • standard math Solver complexity formulas (2)-(5) from [18] and [16] correctly characterize runtime.
    The paper's acceleration claims inherit these prior formulas; no new solver-internal analysis is provided.

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Cite this review

Pith. "Pith review of HAQA: A Hardware-Guided and Fidelity-Aware Strategy for Efficient Qubit Mapping Optimization." pith.science (2026). https://pith.science/paper/5PWPLCVA

@misc{pith2026250416468,
  author       = {Pith},
  title        = {Pith review of: HAQA: A Hardware-Guided and Fidelity-Aware Strategy for Efficient Qubit Mapping Optimization},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/5PWPLCVA}},
  note         = {Machine review of arXiv:2504.16468}
}
read the original abstract

Quantum algorithms rely on quantum computers for implementation, but the physical connectivity constraints of modern quantum processors impede the efficient realization of quantum algorithms. Qubit mapping, a critical technology for practical quantum computing applications, directly determines the execution efficiency and feasibility of algorithms on superconducting quantum processors. Existing mapping methods overlook intractable quantum hardware fidelity characteristics, reducing circuit execution quality. They also exhibit prolonged solving times or even failure to complete when handling large-scale quantum architectures, compromising efficiency. To address these challenges, we propose a novel qubit mapping method HAQA. HAQA first introduces a community-based iterative region identification strategy leveraging hardware connection topology, achieving effective dimensionality reduction of mapping space. This strategy avoids global search procedures, with complexity analysis demonstrating quadratic polynomial-level acceleration. Furthermore, HAQA implements a hardware-characteristic-based region evaluation mechanism, enabling quantitative selection of mapping regions based on fidelity metrics. This approach effectively integrates hardware fidelity information into the mapping process, enabling fidelity-aware qubit allocation. Experimental results demonstrate that HAQA significantly improves solving speed and fidelity while ensuring solution quality. When applied to state-of-the-art quantum mapping techniques Qsynth-v2 and TB-OLSQ2, HAQA achieves acceleration ratios of 632.76 and 286.87 respectively, while improving fidelity by up to 52.69% and 238.28%

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Forward citations

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