Surface Optimization of Superconducting Aluminum Resonators for Robust Quantum Device Fabrication

Alwin Maiwald; Carla Moran-Guizan; Christoph Kutter; Daniela Zahn; Emir Music; Ignaz Eisele; Johannes Weber; Luis Schwarzenbach; Rui N. Pereira; Simon J. K. Lang

REVIEW 3 major objections 5 minor 37 references

Surface Optimization of Superconducting Aluminum Resonators for Robust Quantum Device Fabrication

T0 review · 3 major / 5 minor · reviewed 2026-08-03 · deepseek-v4-flash

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Pith's one-line read Selective removal of surface oxides with HF vapor followed by phosphoric acid reduces dielectric loss in aluminum superconducting resonators by a factor of three, reaching median δ_LP ≈ 5.7×10⁻⁷ (Q ≈ 1.7 million) even after a 24-hour delay

desk verdict A useful process-engineering study with one promising etch recipe and one cautionary negative result, but the headline numbers rest on too few chips to be taken as precisely as stated. read the letter →

arxiv 2601.04082 v3 pith:5WPYLWBE submitted 2026-01-07 quant-ph cond-mat.mtrl-sciphysics.app-ph

Simon J. K. Lang , Ignaz Eisele , Alwin Maiwald , Emir Music , Luis Schwarzenbach , Carla Moran-Guizan , Johannes Weber , Daniela Zahn

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Thomas Mayer Rui N. Pereira Christoph Kutter

This is my paper · ORCID

classification quant-phcond-mat.mtrl-sciphysics.app-ph

keywords aluminumresonatorssuperconductingqubitssurfaceoxideremovaltwo-levelsystemsdielectriclossHFvaporetchphosphoricacidcoplanarwaveguide

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper sets out to find post-processing surface treatments that keep aluminum superconducting resonators free of lossy oxides when cooldown is delayed by about a day, as happens in industrial fabrication. It claims that a simple two-step chemical etch—HF vapor to strip silicon dioxide and phosphoric acid to strip aluminum oxide—cuts the low-power dielectric loss by a factor of three compared with untreated chips, reaching a median quality factor around 1.7 million. It also reports that fluorine passivation protects aluminum against buffered oxide etch but raises dielectric loss, and that remote oxygen plasma gives only a modest improvement. The underlying physics is that surface oxides host two-level systems that dissipate energy; removing the oxides should therefore improve qubit coherence times. A sympathetic reader would care because the result offers a wafer-compatible, chemistry-only route to robust qubit fabrication without relying on immediate cryostat cooldown.

What carries the argument

The carrying mechanism is the selective two-step oxide etch: HF vapor strips silicon dioxide with high selectivity to silicon and aluminum, while undiluted phosphoric acid etches aluminum oxide with high selectivity to silicon and SiO₂. Doing both in sequence removes the oxide layers that host two-level systems (TLS)—atomic-scale defects that absorb microwave energy at low power. The performance metric that carries the comparison is the low-power loss δ_LP, extracted by fitting the photon-number dependence of the internal quality factor to a standard TLS model. The combination of a single-wafer sample set and a 24-hour delay before cooldown is what makes the result relevant to production-sty

What would settle it

Prepare at least ten resonator chips per condition from multiple wafers, randomize which chips receive the HF + phosphoric acid etch, and measure δ_LP blind. If the treated median is not separated from untreated by roughly a factor of three, or if one untreated wafer matches the treated level, the claimed ordering and factor would not hold.

Watch

Extended reading notes

Core claim

On the paper's own terms, the central discovery is that selective chemistry can remove each surface oxide independently without attacking the metal: HF vapor removes SiO₂ while leaving Al₂O₃, and undiluted phosphoric acid removes Al₂O₃ while leaving Si. Applied sequentially to otherwise untreated resonator chips and followed by a 24-hour wait in ambient air before cooldown, this two-step etch lowered the median low-power dielectric loss from the untreated level by roughly a factor of three, down to δ̃_LP = 5.7 × 10⁻⁷ (Q ≈ 1.7M), with the lower quartile at 5.2 × 10⁻⁷ (Q = 1.9M). The authors attribute the improvement to the removal of TLS-hosting oxides, consistent with the established picture

Load-bearing premise

The result rests on treating chips cut from the same 200 mm wafer as geometrically identical, so the observed factor-of-three loss gap is attributed to the chemical treatment rather than to chip-to-chip variation—and each condition uses only two chips, with some lost.

Editorial extensions

If this is right

Aluminum resonator chips can be post-treated with a simple wet/vapor etch and still reach Q ≈ 1.7 million after sitting in air for 24 hours, a realistic industrial scheduling window.
The factor-of-three loss reduction implies that surface oxides are a dominant, removable source of TLS loss in these devices, not an intrinsic material limit.
Fluorinated aluminum surfaces can survive BOE without visible damage, which could enable full-chip BOE treatment in devices that combine Al junctions with Nb or Ta resonators—though at a measurable loss penalty.
The same HF + phosphoric acid sequence may be applied to other Al-based circuits, including transmon qubit electrodes, with potential coherence gains.
Remote oxygen plasma offers only a marginal improvement and high-power direct plasma worsens loss, so process engineers should avoid energetic ion bombardment of the resonator surfaces.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

A natural extension not tested in the paper is whether the two-step etch also reduces high-power loss or whether it only removes TLS losses, which would point toward a different set of residual loss mechanisms.
The 24-hour delay result suggests the etched surfaces re-oxidize slowly enough to remain beneficial; extending the test to longer or humid delays would map out how long the treatment stays effective in real fabs.
The chemical etch might be combined with the remote oxygen plasma or with argon-milling steps to push Q further, although the paper does not demonstrate such a stack.
If the loss reduction transfers to qubit T1, the same etch could let manufacturers decouple resonator and qubit fabrication timing, easing multi-chip packaging workflows.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Simon, here's my take on arXiv:2601.04082. It's a solid process-engineering study, not a breakthrough in loss physics. The genuinely new bits are the fluorine passivation negative result and the direct/remote oxygen plasma comparison, plus a selective oxide removal sequence that looks promising for wafer-scale Al fabrication with a fixed 24-hour ambient delay. The methods are standard, but the systematic comparison is useful.

The paper does well where it sticks to empirical comparison. XPS confirms fluorine incorporation scales with Ar mill time, and the loss data track that trend. The remote oxygen plasma mildly reduces loss and the high-power direct plasma makes things worse, which is consistent with ion damage. The combined HF vapor + phosphoric acid etch gives the best median loss, and the individual etches each give a factor of two. That ordering is physically sensible under the oxide/TLS picture, and the negative fluorine result is a useful caution for people thinking about fluorinated passivation.

Where it gets soft: the headline factor-of-three rests on two chips per condition, some lost. The paper treats chips as geometrically identical based on [28], but that doesn't bound within-wafer variation in surface oxide composition or contamination. Since resonators on the same chip share history, the IQRs in Fig. 8 overstate the statistical support. Two chips cannot separate treatment effects from chip-to-chip luck. The paper should report per-chip medians and ideally more chips. Also, there is no zero-delay control, so "preserves low dielectric loss for a 24-hour delay" is not directly supported—what the data show is that after a 24-hour delay, the treated samples have lower loss than untreated ones with the same delay. That's still useful, but the wording overshoots. The abstract/body numbers are actually consistent if you read "median" carefully, but the abstract introduces δ_TLS without defining it, and the body's emphasis on the lower quartile is a bit cherry-picked.

The stress-test worry about a chip-selection artifact is not proven, but the data cannot rule it out. That's a correctable experimental-design gap, not a fatal flaw. The direction of the effect is plausible and consistent with the literature.

I would engage with this paper: send it to a referee who cares about fabrication reproducibility, and ask for more chips and a zero-delay control. The fluorine negative result and the remote/direct oxygen contrast alone justify the read.

Referee Report

3 major / 5 minor

Summary. The paper investigates post-fabrication surface treatments for aluminum coplanar-waveguide resonators subject to a controlled 24-hour ambient delay before cryogenic measurement. Three approaches are compared: oxygen plasma passivation, fluorine passivation via Ar-milling plus CF4 plasma, and selective chemical etching with HF vapor and/or H3PO4. The central claim is that sequential application of HF vapor and phosphoric acid removes SiO2 and Al2O3 selectively, reducing TLS-dominated low-power loss by a factor of about three relative to untreated samples, reaching δ~LP ≈ 5.7×10^-7 and QLP ≈ 1.7–1.9 million in the single-photon regime. The paper also reports that fluorination increases loss while passivating Al against BOE, and that remote oxygen plasma modestly reduces loss. The measurements use the standard TLS loss model to extract δ_LP from S21 data on nine resonators per chip, with two chips per treatment condition.

Significance. If the central claim holds, this is a practically valuable result: a simple, wafer-compatible HF-vapor/H3PO4 etch sequence would mitigate oxide-related TLS loss in Al resonators even after a 24-hour delay, directly addressing an industrial fabrication constraint. The study is systematic in its comparison of several treatments, uses a single wafer to suppress wafer-to-wafer variability, includes XPS verification of fluorination, and is consistent with the established picture of TLS losses from surface oxides. However, the quantitative factor-of-three improvement and the robustness claim rest on a small number of chips per condition and the absence of a zero-delay control, so the experimental support is currently weaker than the abstract's definitive wording implies.

major comments (3)

[§IV, Fig. 8] second major comment
[§III-C, abstract] The abstract and conclusion claim that the etch sequence 'preserves low dielectric losses for a 24-hour delay before cooldown.' No zero-delay or shorter-delay control is reported, so the data only show that the treated samples are lower-loss than untreated samples after the same delay. It does not demonstrate that delay does not degrade the treated surface. A control with immediate cooldown (or at least a second delay time) is needed to support the 'robust to delay' conclusion.
[§IV-C and abstract] There is a numerical inconsistency in the headline result. The posted abstract reports δ~LP = 5.7×10^-7 and QLP ≈ 1.7 million, while the full-text abstract and §IV-C state δLP = 5.2×10^-7 and QLP = 1.9 million, with 5.2×10^-7 described as the lower quartile. The authors should reconcile these numbers and consistently report the median, quartiles, and corresponding quality factors.

minor comments (5)

[§II, Eq. (1)] The fit parameters n_c, β, and δ_HP are not listed or bounded. Since the extracted δ_LP is the key quantity, at least a brief statement of fit stability and uncertainty would help.
[§IV-A] The remote-oxygen-plasma improvement is described as 'approximately 50%' but the IQRs overlap substantially. This claim should be softened or accompanied by significance testing.
[§III-B] The XPS data in Fig. 5 show atomic fractions after the samples were milled for 1 min before XPS; the distinction between surface and bulk composition should be clarified.
[§IV-C] The phrase 'reduced the loss by a combined factor of three' is ambiguous: is the factor relative to the untreated median, or to the medians of the individual etches? Please state the comparison explicitly.
[General] A few minor grammatical issues and missing articles appear throughout, and the abstract's first sentence would benefit from rewording for clarity.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: measured-loss comparison with standard TLS fit; no prediction reduces to fitted input.

full rationale

The paper makes no derivation-to-conclusion circular step. The central quantitative quantity, δ_LP, is an empirical fit parameter obtained from measured S21 data using the standard TLS model in Eq. (1) (Section II), and it is not used as an input to define any treatment. The key claim—that combined HF-vapor and H3PO4 etching reduces δ_LP relative to untreated samples—is a direct inter-group comparison of measured low-power losses (Section IV-C, Fig. 8), not a quantity forced by construction. The self-citations [17] and [28] supply process parameters and a fabrication-reproducibility assertion; they do not define the measured loss ordering or constitute an unverified load-bearing uniqueness claim. Even the 'geometrically identical' assumption supported by [28] concerns wafer-processing reproducibility rather than a derivation that presupposes the result. The statistical weakness (two chips per condition, lost samples, chip-to-chip variability) is an evidential/correctness concern, not circularity. The abstract/body numerical inconsistency is reportorial and does not affect the derivation chain. Therefore no significant circularity is present.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

The central result is an empirical inter-group comparison, not a derivation. The only fitted content is the standard TLS saturation model (Eq.1) and its nuisance parameters. The statistical load is carried by the single-wafer equivalence assumption and small sample sizes. No new particles, mediators, or physical entities are introduced.

free parameters (3)

n_c (critical photon number) = per-resonator, not reported
Fitted in Eq.(1) to model power saturation of TLS loss; the extracted δ_LP depends on this scale.
β (TLS saturation exponent) = per-resonator, not reported
Free exponent in Eq.(1); no independent measurement is provided.
δ_HP (high-power loss floor) = per-resonator, not reported
Fitted constant offset at high photon number in Eq.(1).

assumptions (4)

domain assumption Eq.(1) describes dielectric loss with a broad TLS distribution and T→0
Taken from Martinis et al. [22]; all δ_LP values are conditional on this model.
domain assumption Chips from one 200 mm wafer are geometrically and electrically equivalent
Stated in §IV; with two chips per treatment, wafer inhomogeneity would confound the comparison.
domain assumption XPS composition after 1 min Ar milling is representative of the resonator surface that determines loss
Used to link F content (Fig. 5) to resonator loss (Fig. 6); XPS and cryogenic measurements were performed on different chips.
domain assumption Removing SiO2 and Al2O3 reduces TLS loss
Well-established in cited refs [14], [15], [22]; the post-etch improvement is interpreted through this lens.

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Cite this review

Pith. "Pith review of Surface Optimization of Superconducting Aluminum Resonators for Robust Quantum Device Fabrication." pith.science (2026). https://pith.science/paper/5WPYLWBE

@misc{pith2026260104082,
  author       = {Pith},
  title        = {Pith review of: Surface Optimization of Superconducting Aluminum Resonators for Robust Quantum Device Fabrication},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/5WPYLWBE}},
  note         = {Machine review of arXiv:2601.04082}
}

abstract

Aluminum (Al) remains the central material for superconducting qubits, and considerable effort has been devoted to optimizing its deposition and patterning for quantum devices. However, post-processing strategies focused on oxide removal of niobium (Nb) and tantalum (Ta) -based resonators using buffered oxide etch (BOE), which can not be used for Al. This challenge becomes particularly relevant for industry-scale fabrication with multi-chip bonding, where delays between sample preparation and cooldown require surface treatments that preserve low dielectric loss during extended exposure to ambient conditions. In this work, we investigate surface modification approaches for Al resonators subjected to a 24-hour delay prior to cryogenic measurement. Passivation using self-limiting oxygen and fluorine chemistries was evaluated utilizing different plasma processes. Remote oxygen plasma treatment reduced dielectric losses, in contrast to direct oxygen plasma. A fluorine-based plasma process was developed that passivated the Al surface for subsequent BOE treatment. However, the fluorine content in the surface resulted in higher loss, identifying fluorine as an unsuitable passivation material for Al resonators. Above all, selective oxide removal using HF (hydrogen fluoride) vapor and phosphoric acid yielded median dielectric losses as low as $\tilde{\delta}_\mathrm{LP} = 5.7 \times 10^{-7}$ ($Q_\mathrm{LP} \approx 1.7\,\mathrm{M}$) with $\tilde{\delta}_\mathrm{TLS} = 3.6 \times 10^{-7}$ ($Q_\mathrm{TLS} \approx 2.8\,\mathrm{M}$) in the single photon regime. Selective oxide removal provides a promising pathway for robust Al-based qubit fabrication, as it preserves low dielectric losses for a 24-hour delay before cooldown.

Figures

Figures reproduced from arXiv: 2601.04082 by the authors.

**Figure 2.** Exemplary plot of δ vs. photon number with measured data (blue) from a 4.36 GHz resonator and a fit using Eq. (1) (red). This data processing was performed for each resonator individually, while the spread of δLP was statistically analyzed [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗

**Figure 3.** Schematic representation of the different post [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗

Figures from the paper (4 more)

**Figure 5.** Figure 5: Atomic composition versus Ar ion milling duration [PITH_FULL_IMAGE:figures/full_fig_p004_5.png]

**Figure 6.** Figure 6: Low-power loss δLP of fluorinated samples for different Ar ion-milling durations. To evaluate whether fluorine incorporation is directly responsible for the increased loss, additional post-etching using BOE or HF was performed in order to remove potential Si trench da…

**Figure 8.** Figure 8: Low-power loss after HF, phosphoric acid, and com [PITH_FULL_IMAGE:figures/full_fig_p005_8.png]

**Figure 7.** Figure 7: (a) Effect of BOE and HF post-etching on fluorinated [PITH_FULL_IMAGE:figures/full_fig_p005_7.png]

Discussion (0). Continue with ORCID to comment.

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Reviewed August 3, 2026 · model on record in the stance chip above.

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