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Hypervisor Extension for a RISC-V Processor

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arxiv 2406.17796 v1 pith:6LOPVQTO submitted 2024-06-12 cs.AR

Jaume Gauchola , JuanJosé Costa , Enric Morancho , Ramon Canal , Xavier Carril , Max Doblas , Beatriz Otero , Alex Pajuelo
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Eva Rodríguez Javier Salamero Javier Verdú
This is my paper · ORCID
classification cs.AR
keywords extensionhypervisorprocessorrisc-vbriefdescribedescribesdesign
verification ladder T0 review T1 audit T2 compute T3 formal
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This paper describes our experience implementing a Hypervisor extension for a 64-bit RISC-V processor. We describe the design process and the main required parts with a brief explanation of each one.

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Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Advancing Cloud Computing Capabilities on gem5 by Implementing the RISC-V Hypervisor Extension

    cs.AR 2024-11 conditional novelty 6.0 of 10

    The paper reports a working implementation of the RISC-V H hypervisor extension in gem5, validated by booting Xvisor with guest Linux and by running nine MiBench workloads with and without a VM.

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