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QPU-System Co-Design for Quantum HPC Accelerators

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arxiv 2208.11449 v4 pith:7TBFXHUN submitted 2022-08-24 cs.AR quant-ph

classification cs.ARquant-ph
keywords quantumco-designinfluenceqpusacceleratorsdeviceslimitationsphysical
verification ladder T0 review T1 audit T2 compute T3 formal

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The use of quantum processing units (QPUs) promises speed-ups for solving computational problems, but the quantum devices currently available possess only a very limited number of qubits and suffer from considerable imperfections. One possibility to progress towards practical utility is to use a co-design approach: Problem formulation and algorithm, but also the physical QPU properties are tailored to the specific application. Since QPUs will likely be used as accelerators for classical computers, details of systemic integration into existing architectures are another lever to influence and improve the practical utility of QPUs. In this work, we investigate the influence of different parameters on the runtime of quantum programs on tailored hybrid CPU-QPU-systems. We study the influence of communication times between CPU and QPU, how adapting QPU designs influences quantum and overall execution performance, and how these factors interact. Using a simple model that allows for estimating which design choices should be subjected to optimisation for a given task, we provide an intuition to the HPC community on potentials and limitations of co-design approaches. We also discuss physical limitations for implementing the proposed changes on real quantum hardware devices.

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  1. Improving and benchmarking NISQ qubit routers

    quant-ph 2025-02 conditional novelty 4.0 of 10

    A SABRE heuristic that keeps only the basic and decay terms outperforms lookahead-based routers in fidelity for larger NISQ devices under a thermal relaxation noise model.

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