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REVIEW 4 major objections 6 minor 1 cited by

Apple vs. Oranges: Evaluating the Apple Silicon M-Series SoCs for HPC Performance and Efficiency

T0 review · 4 major / 6 minor · reviewed 2026-08-08 · deepseek-v4-flash

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Pith's one-line read The Apple Silicon M1–M4 chips, despite weak FP64 GPU support, deliver up to 2.9 FP32 TFLOPS, close-to-peak memory bandwidth, and more than 200 GFLOPS per watt, making them a viable energy-efficient platform for single-precision HPC…

desk verdict Useful four-generation Apple Silicon benchmark, but the headline power-efficiency claims rest on the very tool the authors admit is unfit for cross-device comparison. read the letter →

arxiv 2502.05317 v2 pith:7XYZ6A4F submitted 2025-02-07 cs.AR

Paul Hübner , Andong Hu , Ivy Peng , Stefano Markidis This is my paper · ORCID
classification cs.AR
keywords AppleSiliconM-SeriesSoCHPCunifiedmemoryFP32energyefficiencyMetalGEMM
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to establish that Apple's M-Series SoCs (M1, M2, M3, M4) are a viable platform for energy-efficient high-performance computing, at least for single-precision workloads. It argues this by building and running custom STREAM and GEMM benchmarks that measure memory bandwidth, FP32 compute throughput, and power draw. The measured results show up to 2.9 FP32 TFLOPS on the M4, unified-memory bandwidth close to the theoretical peak, and more than 200 GFLOPS per watt for all four chips. The point of caring is practical: if these numbers hold, a class of low-power commodity devices can serve real HPC tasks without the power and cooling demands of traditional accelerators.

What carries the argument

The argument rests on a custom benchmark suite: a GPU-port of the STREAM memory-bandwidth benchmark written in Metal Shading Language and Objective-C++, plus a family of GEMM implementations (naive C++, Accelerate/BLAS vDSP, OpenMP-tiled, Metal naive shader, Cutlass-style tiled shader, and Metal Performance Shaders) covering CPU and GPU paths. Power is measured with Apple's powermetrics utility, sampled around the GEMM execution. These measurements are what turn the architectural claims about unified memory, AMX, and the TBDR GPU into quantitative statements about bandwidth, FLOPS, and efficiency.

What would settle it

A direct wall-plug power measurement of the same GEMM runs, using a physical power meter instead of powermetrics, that showed any of the four chips falling below 200 GFLOPS per watt, or that reversed the paper's M1-to-M4 efficiency ordering, would falsify the paper's efficiency claim as stated.

Watch

Extended reading notes

Core claim

Across four generations of Apple Silicon, the paper measures steady generational improvement in FP32 throughput, with the GPU pulling ahead of the CPU starting with the M2: peak MPS-based GEMM performance climbs from 1.36 TFLOPS on the M1 to 2.24 on the M2, 2.47 on the M3, and 2.9 TFLOPS on the M4, reaching 63% of the M4's theoretical peak. STREAM results show CPU and GPU both reaching roughly 85-100% of theoretical memory bandwidth, with the M4 at about 100-103 GB/s. Power dissipation during matrix multiplication ranges from a few watts to about 20 watts, and the power efficiency of GPU-MPS crosses 200 GFLOPS per watt on every chip, about an order of magnitude above the paper's reported Green500 and A100 reference points. The paper positions these chips not as direct competitors to systems like the Nvidia GH200, which reaches 41 TFLOPS on CUDA cores, but as a distinct, power-efficient category of their own.

Load-bearing premise

The central efficiency claim depends on Apple's powermetrics software estimates of CPU and GPU power being accurate enough to compare the four chips against each other and against external HPC efficiency figures, even though Apple advises against using powermetrics for cross-device comparisons.

Editorial extensions

If this is right

  • If the M4's measured 2.9 FP32 TFLOPS is representative, Apple Silicon is a credible platform for single-precision HPC kernels, despite lacking native FP64 GPU support.
  • If all four chips consistently exceed 200 GFLOPS per watt, then power-constrained or thermally constrained installations could run useful FP32 workloads on M-Series hardware at a fraction of the energy budget of discrete accelerators.
  • If the unified memory delivers near-theoretical bandwidth to both CPU and GPU, data-movement-heavy HPC codes could avoid explicit PCIe-style transfers and still see high throughput.
  • If the GH200 comparison is taken at face value, the M-Series is not a replacement for high-end HPC accelerators, but a complementary low-power option for certain workloads.
  • If the power efficiency measurements are accurate, the gap between Apple's GPU-MPS and the less optimized shaders suggests that software optimization, not raw silicon, is the main lever for reaching high GFLOPS per watt.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The paper leaves the Neural Engine untested, so a direct comparison of the Neural Engine's FP16 throughput per watt against Nvidia Tensor Cores would be the natural next step for mixed-precision HPC. (Editorial inference, not a paper claim.)
  • Because power measurements come from powermetrics rather than wall-plug meters, the absolute GFLOPS-per-watt figures should be treated as estimates; a direct instrumented measurement could shift the ranking among the four chips. (Editorial caution grounded in the paper's own stated limitation.)
  • The strong efficiency at small power envelopes suggests that a cluster of many M-Series nodes could be an interesting testbed for energy-aware scheduling, but the paper does not evaluate multi-node networking or distributed memory behavior. (Editorial extension.)
  • The M4's advantage over earlier chips in both FLOPS and efficiency hints that future M-series releases may narrow the gap to traditional HPC accelerators, but extrapolating beyond the measured four generations is speculative. (Editorial inference.)
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. This paper evaluates four Apple Silicon M-Series SoCs (M1, M2, M3, M4) for HPC-relevant workloads. It provides an architectural survey, custom STREAM and GEMM benchmarks written in Metal Shading Language and Objective-C++, and power/efficiency measurements using Apple's powermetrics tool. The main empirical claims are: CPU and GPU memory bandwidth reach roughly 85–100% of theoretical peak (up to about 100 GB/s on the M4), FP32 GPU performance reaches 2.9 TFLOPS on the M4, and all four chips exceed 200 GFLOPS/W for the best GPU implementation. These numbers are compared against an Nvidia GH200, Green500, A100, and RTX 4090. The paper concludes that Apple Silicon offers a power-efficient alternative for single-precision HPC workloads, while acknowledging limitations in FP64 support and in power-measurement accuracy.

Significance. If the measurements were fully validated, the paper would provide a useful early data point on Apple Silicon M-Series for HPC, with the combination of architectural description, standardized STREAM/GEMM benchmarks, and open-source code being a valuable community resource. The memory-bandwidth and raw-FLOPs results are plausible and internally consistent with the documented hardware specifications. However, the headline efficiency claim of 'more than 200 GFLOPS per Watt' depends on power numbers that the paper itself says are software estimates that Apple advises against using for cross-device comparisons. Since the power-efficiency message is central to the paper's conclusion, the significance is conditional on either stronger power validation or a substantially more cautious framing of the efficiency comparisons.

major comments (4)
  1. [Section 5.3, Figure 4] The central power-efficiency claim rests on powermetrics estimates that the paper itself cautions against. Section 5.3's HPC Perspective states that 'powermetrics's results are software estimates, and Apple explicitly advises against comparing them to different devices,' yet Figure 4 and Section 7 use these numbers to rank M1 through M4 by efficiency and to compare against Green500, A100, and RTX 4090 figures that use different power boundaries. No wall-power measurement or external-meter calibration is provided. At minimum, the cross-device quantitative efficiency comparisons must be removed or explicitly labeled as unvalidated estimates, and the abstract's 'competitive power-efficient alternative' claim should be correspondingly qualified.
  2. [Table 3, Section 4] The four SoCs are not compared in equivalent hosts: the M1 and M3 are passively cooled MacBook Airs while the M2 and M4 are Mac minis, with different cooling, chassis, memory sizes, and macOS versions. This confounds generational SoC differences with device-level thermal and power-management differences. The observed M1–M4 efficiency ordering in Figure 4 should be attributed to the specific devices tested, not to the SoCs generally; the paper should either use matched chassis or explicitly restrict all comparative claims to these particular machines.
  3. [Section 4, Section 5.1, Figure 4] Only maximum values are reported: STREAM runs were repeated ten or twenty times but only the maximum is used, and each GEMM experiment was repeated five times with no variance, confidence intervals, or error bars. Given the small repetition count, differences such as the M2 CPU anomaly in Section 5.1 and the M3-vs-M4 efficiency ranking in Figure 4 may be within run-to-run noise. The paper should report dispersion (e.g., standard deviation or min–max ranges) or otherwise demonstrate that reported differences are reproducible.
  4. [Section 5.2, HPC Perspective; Section 7] The paper acknowledges in Section 5.2 that comparing FP32 results to GH200 Tensor Core TF32 results is 'unfair,' but Section 7 still compares the M4 FP32 result against RTX 4090 'tensor core performance' and A100 'mma' figures, and the Green500 comparison in Section 5.3 implicitly compares against system-level mixed-precision workloads. These are apples-to-oranges comparisons that mix precision formats and power boundaries; they should be either removed or replaced with directly comparable FP32/FP64 measurements, or explicitly presented only as rough, non-quantitative context.
minor comments (6)
  1. [Section 7] There is a typo: 'Nividia GH200' should be 'Nvidia GH200'.
  2. [Section 5.1, HPC Perspective] The phrase '92 GB/s% (M3 CPU, 92%)' contains a malformed percentage; it should read '92 GB/s (92% of theoretical, M3 CPU)'.
  3. [Section 5.3] The phrase 'A-Series chips' should presumably be 'M-Series chips' in the sentence about CPU-Accelerate power efficiency.
  4. [Table 1 and Section 2.1] Table 1 lists L1 cache as 128 KB (P)/64 KB (E), while Section 2.1 says 'L1 caches (e.g., 192 KB per performance core)'; these values should be reconciled or the discrepancy explained.
  5. [Figures 2–4] The figure legends and axis labels are sometimes difficult to read, especially the exponent notation (e.g., '10□1'), and the order of legend entries does not match the order of the plotted series; please make the figures more legible and self-contained.
  6. [References] Several references have inconsistent formatting, including missing page numbers and author lists truncated with 'and et al.'; the reference list should be cleaned up.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: all central claims are direct measurements with external reference points; the powermetrics caveat is a validity limitation, not circularity.

full rationale

This paper is an empirical benchmark study with no fitted parameters, no inverse problem, and no derivation that reduces to its own inputs. FP32 performance is measured directly via GEMM kernels, memory bandwidth is measured directly via STREAM kernels, and efficiency is computed as measured FLOPs divided by measured power. The only internal tool caveat—powermetrics results are software estimates and Apple advises against comparing them across devices (Section 5.3 HPC Perspective)—concerns measurement validity and cross-device comparability, not circularity: the efficiency number is not defined in terms of the paper's conclusion, nor is the conclusion encoded in the measurement. The self-references [20] and [22] are cited for the provenance of the CUDA/HIP STREAM port, and [14], [19], and [21] are cited for background or comparison data; none is invoked as an authority that forces the paper's central claim. External anchors such as the GH200 using official Nvidia HPC benchmarks, Green500, A100, and RTX 4090 literature provide independent reference points. No equation equates a prediction with an input, no fitted parameter is renamed as a result, and no uniqueness theorem from the authors is used to declare a choice forced. Therefore no circularity is present. The powermetrics concern is a legitimate correctness and measurement limitation, but it does not make the derivation circular.

Assumptions & free parameters 0 free parameters · 2 assumptions · 0 invented entities

The paper's central efficiency claims depend on a domain assumption about powermetrics measurements and a representativeness assumption about the four host devices. There are no fitted free parameters and no invented entities; the benchmarks are standard HPC microbenchmarks.

assumptions (2)
  • domain assumption Apple's powermetrics power estimates are accurate enough for cross-device efficiency comparisons.
    The paper computes GFLOPS per watt using powermetrics and compares across M1-M4 and against Green500 and A100 figures (Section 5.3), while the HPC Perspective box states Apple advises against comparing these measurements to different devices.
  • domain assumption The four test devices (M1 MacBook Air, M2 Mac mini, M3 MacBook Air, M4 Mac mini) are representative of their respective SoC generations.
    Table 3 lists different host devices with different cooling (passive vs fan) and power strategy, so power and sustained performance may reflect the machine rather than the chip generation.

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Cite this review

Pith. "Pith review of Apple vs. Oranges: Evaluating the Apple Silicon M-Series SoCs for HPC Performance and Efficiency." pith.science (2026). https://pith.science/paper/7XYZ6A4F

@misc{pith2026250205317,
  author       = {Pith},
  title        = {Pith review of: Apple vs. Oranges: Evaluating the Apple Silicon M-Series SoCs for HPC Performance and Efficiency},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/7XYZ6A4F}},
  note         = {Machine review of arXiv:2502.05317}
}
read the original abstract

This paper investigates the architectural features and performance potential of the Apple Silicon M-Series SoCs (M1, M2, M3, and M4) for HPC. We provide a detailed review of the CPU and GPU designs, the unified memory architecture, and coprocessors such as Advanced Matrix Extensions (AMX). We design and develop benchmarks in the Metal Shading Language and Objective-C++ to assess FP32 computational and memory performance. We also measure power consumption and efficiency using Apple's powermetrics tool. Our results show that the M-Series chips offer up to 100 GB/s memory bandwidth, and significant generational improvements in computational performance, with up to 2.9 FP32 TFLOPS on the M4. Power consumption varies from a few Watts to 10-20 Watts, with more than 200 GFLOPS per Watt efficiency of GPU and accelerator reached by all four chips. Despite limitations in FP64 support on the GPU, the M-Series chips demonstrate strong potential for energy-efficient HPC applications. While existing HPC solutions such as the Nvidia Grace-Hopper superchip outperform Apple Silicon in both memory bandwidth and computational performance, we see that the M-Series provides a competitive power-efficient alternative to traditional HPC architectures and represents a distinct category altogether -- forming an apples-to-oranges comparison.

Figures

Figures reproduced from arXiv: 2502.05317 by the authors.

Figure 1
Figure 1. STREAM benchmark results of each processor. The line represents the theoretical bandwidth, and CPU/GPU implementations [PITH_FULL_IMAGE:figures/full_fig_p009_1.png] view at source ↗
Figure 2
Figure 2. GFLOPS for all implementations and matrices sizes. [PITH_FULL_IMAGE:figures/full_fig_p010_2.png] view at source ↗
Figure 3
Figure 3. Power utilization of each implementation varying matrix size. [PITH_FULL_IMAGE:figures/full_fig_p011_3.png] view at source ↗
Figures from the paper (1 more)
Figure 4
Figure 4. Figure 4: Power efficiency in GFLOPS per Watt, higher is better. [PITH_FULL_IMAGE:figures/full_fig_p012_4.png]

Discussion (0). Continue with ORCID to comment.

Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. TriADA: Massively Parallel Trilinear Matrix-by-Tensor Multiply-Add Algorithm and Device Architecture for the Acceleration of 3D Discrete Transformations

    cs.DC 2025-06 conditional novelty 4.0 of 10

    The paper proposes a triple-stage outer-product algorithm and an isomorphic 3D mesh architecture that computes separable 3D orthogonal transforms in N1+N2+N3 time steps.

Reference graph

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