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REVIEW 3 major objections 6 minor 87 references

Enabling Low-Cost Secure Computing on Untrusted In-Memory Architectures

T0 review · 3 major / 6 minor · reviewed 2026-08-10 · deepseek-v4-flash

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Pith's one-line read Secret sharing and garbled circuits let a TEE outsource linear and nonlinear computation to untrusted PIM hardware, with speedups up to 14.66x over a secure CPU while preserving confidentiality and integrity.

desk verdict First real-hardware MPC-secure PIM evaluation is a useful systems contribution, but the headline integrity guarantee for nonlinear computation does not hold as stated. read the letter →

arxiv 2501.17292 v2 pith:ANPQ4NSJ submitted 2025-01-28 cs.CR

Sahar Ghoflsaz Ghinani , Jingyao Zhang , Elaheh Sadredini This is my paper · ORCID
classification cs.CR
keywords processing-in-memorysecurecomputationmulti-partyarithmeticsecretsharingYao'sgarbledcircuitstrustedexecutionenvironmentUPMEMmemorywall
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims that a Trusted Execution Environment (TEE) can safely offload bandwidth-hungry computation to off-chip Processing-in-Memory (PIM) hardware that is explicitly outside the trusted computing base. It does this by splitting every private value into an arithmetic secret share: the PIM receives a ciphertext share masked by a one-time pad and works on that, while the TEE or an offline precomputation phase handles the pad share. Nonlinear functions, which arithmetic sharing cannot handle, are outsourced by switching to Yao's garbled circuits with a circuit-friendly sigmoid approximation. On real UPMEM hardware this yields up to 14.66x, 9.80x, 2.64x, and 5.85x speedups over a secure CPU for MLP inference, DLRM inference, linear regression training, and logistic regression training, with about 4% overhead relative to an insecure PIM. If correct, this means secure computing no longer has to give up the memory-wall benefits of PIM.

What carries the argument

The load-bearing mechanism is arithmetic secret sharing in counter mode: each plaintext element $P_i$ is split as $C_i = P_i - R_i$, with $R_i$ a one-time pad generated inside the TEE. The PIM evaluates the linear kernel (GEMV, embedding lookup, dot product) over the ciphertext share $C_i$, while the CPU handles the pad share $R_i$; adding the partial results reconstructs the answer. Precomputation moves the CPU's share of the work offline, so the CPU decryption and merge stay lightweight. For nonlinear functions, the protocol switches to Yao's garbled circuits—a two-party Boolean-circuit evaluation—using a piecewise-linear approximation of sigmoid that is cheap to express as a circuit. Linear modular hashing tags provide the integrity check for the linear portions.

What would settle it

A concrete test: instrument a DPU to flip bits in the activation output (or return a wrong Yao-circuit result) during logistic regression training, then check whether the verification step flags it. If such tampering passes undetected, the nonlinear-integrity claim fails. A second check is to measure logistic regression or MLP accuracy on standard public datasets using the circuit-friendly sigmoid approximation and compare with the exact sigmoid; the claim of negligible accuracy loss stands only if the gap is negligible.

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Extended reading notes

Core claim

The central discovery is that the arithmetic secret-sharing machinery already used to outsource linear kernels can be extended to nonlinear workloads and to real PIM hardware without letting the CPU's share become the bottleneck. The PIM multiplies masked shares by public weights; the CPU computes the same kernel over one-time pads, either at runtime or precomputed offline; the two partial results are added inside the TEE. For activation functions, the scheme switches to Yao's garbled circuits, where the trusted CPU builds the circuit and both sides feed in their shares. Integrity for the linear parts is checked by linear modular hashing tags computed over the PIM's output, and the paper reports that this verification overhead is small. The paper backs the speedup claim with measurements on a 20-DIMM UPMEM system running MLP, DLRM, linear regression, and logistic regression.

Load-bearing premise

The claim stands or falls on whether a malicious PIM cannot corrupt the nonlinear computation without detection; the paper's own verification uses linear checksums that, by its own statement, cannot verify nonlinear computations, so the integrity guarantee for nonlinear work rests on a cited garbled-circuit protocol rather than a demonstrated check.

Editorial extensions

If this is right

  • A TEE can offload memory-bound linear kernels such as GEMV and embedding lookups to untrusted PIM at close to insecure-PIM speed, because the CPU's share is either generated on the fly or precomputed offline.
  • Nonlinear operations such as sigmoid activation can be included in secure offloading by switching to Yao's garbled circuits, enabling full training loops like logistic regression rather than only linear inference.
  • The speedups hold on real UPMEM hardware, not just simulation, with up to 14.66x over a TEE-only CPU and only about 4% overhead over an insecure PIM for MLP.
  • The same secret-sharing recipe extends to GEMM and convolution by unrolling them into GEMV operations, so CNNs and Transformer attention layers are natural next targets.
  • For workloads where public data is large relative to private data, precomputation removes the CPU bottleneck that limited earlier MPC-on-PIM schemes.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Inference: if the nonlinear-integrity gap is real, the framework's guarantee for nonlinear workloads is confidentiality only; a malicious PIM could bias activations or gradients without detection, silently changing the trained model.
  • Inference: the practical speedup sweet spot is large, memory-resident datasets; the paper's own DLRM results show only 1.53x at a 16 GB table rising to 6.44x at 24 GB, so small problems may not justify the share-splitting overhead.
  • Inference: a testable extension is to apply the same arithmetic-sharing plus garbled-circuit design to a different near-data processor and measure whether the linear checksum catches injected faults in a mixed linear/nonlinear pipeline.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. The paper proposes a framework for securely offloading memory-bound computation from a TEE-protected CPU to untrusted processing-in-memory (PIM) hardware. The approach combines arithmetic secret sharing and counter-mode encryption for linear operations, Yao's garbled circuits for nonlinear operations, linear modular-hash MACs for verification, and an offline precomputation phase to keep the trusted CPU off the critical path. The authors evaluate the scheme on UPMEM hardware for MLP inference, DLRM inference, linear regression training, and logistic regression training, reporting speedups of up to 14.66x, 9.80x, 2.64x, and 5.85x over a secure CPU baseline and a roughly 4% overhead over insecure PIM for the MLP case. The linear computation path is largely inherited from prior work (SecNDP, Slalom) and the measurements are concrete, but the paper's central claim of confidentiality and integrity for nonlinear computation rests on a protocol description and security argument that are not sufficiently developed.

Significance. If the nonlinear-integrity claim can be properly established, this would be a useful systems contribution: it is, to my knowledge, one of the first evaluations of MPC-based secure computation on real PIM hardware, it provides an open-source artifact, and the precomputation optimization directly addresses a known bottleneck in SecNDP when public data dominates private data. The measured speedups over a secure CPU and the small overhead relative to insecure PIM are concrete and reproducible in principle from the artifact. However, the significance is gated by the security claim: the paper promises integrity for nonlinear computation, and the current text delegates that guarantee to citations and to linear checksums that the paper itself says cannot verify nonlinear steps. Without a protocol-level argument or proof for the nonlinear path, the central advertised capability is not established.

major comments (3)
  1. [§5.3.2, §5.4, §5.6] The central claim of integrity for nonlinear computation is not supported. Section 5.4 explicitly states that the linear checksum "cannot be used to verify non-linear computations," and the logistic regression evaluation verifies only after the dot product and after gradient descent, both of which are linear checksums over the data as supplied. If a malicious DPU corrupts the activation output, the subsequent linear computations are internally consistent with the corrupted value, so both checks pass. Section 5.6's "Correctness of Non-linear Computation" is a citation to SecureML, but SecureML's garbled-circuit guarantees are not shown to apply to this single-untrusted-evaluator outsourcing model: an evaluator executing a garbled circuit can return an arbitrary output label, and the paper describes no mechanism for the TEE to authenticate or verify that output. A proof or a concrete protocol-level argument that a malicious PIM cannot deviate from the activation function undetected is required; otherwise the abstract's claim of "maintaining data confidentiality and integrity when outsourcing linear and/or nonlinear computation" is not established.
  2. [§5.3.2] The Yao-based nonlinear protocol is under-specified to the point of being non-auditable. The text says "The TEE computes b1 and b2, constructs the corresponding Garbled Circuit, and securely shares it with the PIM," but computing b1 and b2 requires comparing the activation input u against ±1/2. If the TEE can compute these bits, it already has enough information to evaluate the piecewise-linear activation locally, and it is unclear what secret input the PIM contributes to the garble circuit or how any deviation by the PIM is detected. If, instead, the TEE computes these bits from its own arithmetic share, the paper must specify the comparison protocol and the arithmetic-to-Yao share conversion. The paper also does not state which party learns the garbled-circuit output and what that party is allowed to infer. These omissions make the nonlinear path impossible to reproduce or validate from the manuscript.
  3. [§7, Logistic Regression] The functional correctness of the SecureML activation approximation is asserted by citation rather than demonstrated. The paper states that SecureML shows the GC-friendly sigmoid does not degrade accuracy, but no accuracy or loss result is reported for the logistic regression workloads evaluated here, and the inputs are described as randomly generated. If the approximation materially changes the trained model on realistic data, the claimed support for logistic regression training is not demonstrated. The authors should report accuracy or loss on a real dataset, or at least quantify the approximation error on the evaluated configurations.
minor comments (6)
  1. [§5.2] Section 5.2 refers to "Table 2 summarizes the key notations," but the table is captioned "Table 1: List of Notations"; renumber or correct the cross-reference.
  2. [§6.2] Section 6.2 says the trusted-DPU baseline is "described in Section 5.4," but that baseline is actually described in Section 5.5; the cross-reference should be fixed.
  3. [§7.1] Figures 14(a), 15(a), 16, 17, and 18 use labels such as UPMEM-Precomputation-CV, UPMEM-Enc/Dec-V, and UPMEM-Runtime-A(2Y)-C(V) without defining the suffixes -V and -C(V) in the captions or the text; these variants should be defined precisely.
  4. [§7.1, Logistic Regression] The statement that the design "experiences a 4.91× slowdown compared to UPMEM-Insecure (LUT) but achieves a 4.61× speedup compared to UPMEM-Insecure (non-LUT)" is confusing as written; the authors should clarify which baselines are LUT and non-LUT and explain why the comparison is meaningful.
  5. [Reference [37]] Reference [37] lists "Accessed: 2024-02-30," which is not a valid date; correct it.
  6. [Figure 2] Figure 2 and the surrounding discussion do not state the exact GEMV sizes, matrix/vector dimensions, or SecNDP configuration used to generate the speedup curves; adding this setup would make the claimed CPU-bottleneck behavior reproducible.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the headline speedups are measured, and the security premises are inherited from external prior work, not from the paper's own definitions or fitted parameters.

full rationale

The paper's derivation chain is empirical rather than definitional. The claimed speedups (14.66x, 9.80x, 2.64x, 5.85x) are measured execution-time ratios reported in Section 7.1 against CPU-Secure and other baselines; they are not quantities obtained by fitting a parameter and then renaming it as a prediction. The MPC construction in Sections 5.3-5.4 combines arithmetic secret sharing, counter-mode encryption, linear checksums, and Yao's garbled circuits; Section 5.6 explicitly delegates the cryptographic guarantees to SecNDP, Slalom, and SecureML, which are external prior works and not self-citations. The paper itself flags a real limitation: "Since the verification scheme uses a linear checksum, it cannot be used to verify non-linear computations" (Section 7.1, Logistic Regression performance analysis), and the nonlinear-integrity argument is inherited from SecureML rather than independently proved. That is a correctness and completeness gap, but it is not circular reasoning: the paper does not define its target result in terms of itself, nor does it fit a parameter to the data it then claims to predict. The only self-citations ([44,61,62,83,84,85]) are background PIM-architecture works and do not carry the load of the security or performance claims. No uniqueness theorem is imported from the authors' own prior work, and no ansatz is smuggled in via self-citation. Therefore no circular step can be exhibited, and the appropriate finding is no significant circularity.

Assumptions & free parameters 0 free parameters · 5 assumptions · 0 invented entities

No free parameters are fitted; all reported quantities are measured. The design uses standard TEE/MPC primitives and leans on prior security results (SecNDP, SecureML, Slalom). The main unproven content is the security and accuracy of the nonlinear Yao path on real PIM hardware and the adequacy of linear-only checksum verification for nonlinear steps.

assumptions (5)
  • domain assumption The TEE is fully trusted and all off-chip components, including PIM, are untrusted.
    Section 2 defines the threat model; the scheme's security is conditional on this trust split.
  • domain assumption Arithmetic secret sharing with counter-mode encryption provides the stated confidentiality for linear computations.
    Section 5.6 says this is 'based on the assumptions validated in SecNDP', not re-proven here.
  • domain assumption The Yao's garbled circuit variant used by the authors is correct and private in the PIM/TEE setting.
    Section 5.6 cites SecureML for correctness; the modified TEE trusted-generator path is not formally specified or proved.
  • ad hoc to paper The SecureML piecewise-linear sigmoid approximation does not materially degrade accuracy on the evaluated workloads.
    Introduced in Section 5.3.2 as a GC-friendly activation; the paper does not measure accuracy, relying on SecureML's claim.
  • domain assumption Linear Modular Hashing MACs are collision-resistant and verify linear PIM computations.
    Section 5.4 cites SecNDP and MMH; no new analysis is given for the UPMEM implementation.

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Cite this review

Pith. "Pith review of Enabling Low-Cost Secure Computing on Untrusted In-Memory Architectures." pith.science (2026). https://pith.science/paper/ANPQ4NSJ

@misc{pith2026250117292,
  author       = {Pith},
  title        = {Pith review of: Enabling Low-Cost Secure Computing on Untrusted In-Memory Architectures},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/ANPQ4NSJ}},
  note         = {Machine review of arXiv:2501.17292}
}
abstract

Modern computing systems are limited in performance by the memory bandwidth available to processors, a problem known as the memory wall. Processing-in-Memory (PIM) promises to substantially improve this problem by moving processing closer to the data, improving effective data bandwidth, and leading to superior performance on memory-intensive workloads. However, integrating PIM modules within a secure computing system raises an interesting challenge: unencrypted data has to move off-chip to the PIM, exposing the data to attackers and breaking assumptions on Trusted Computing Bases (TCBs). To tackle this challenge, this paper leverages multi-party computation (MPC) techniques, specifically arithmetic secret sharing and Yao's garbled circuits, to outsource bandwidth-intensive computation securely to PIM. Additionally, we leverage precomputation optimization to prevent the CPU's portion of the MPC from becoming a bottleneck. We evaluate our approach using the UPMEM PIM system over various applications such as Deep Learning Recommendation Model inference and Logistic Regression. Our evaluations demonstrate up to a $14.66\times$ speedup compared to a secure CPU configuration while maintaining data confidentiality and integrity when outsourcing linear and/or nonlinear computation.

Figures

Figures reproduced from arXiv: 2501.17292 by the authors.

Figure 1
Figure 1. (a) TEE-based system. Only on-chip modules (e.g., [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Speedup of the SecNDP security scheme using UPMEM over an insecure CPU for the GEMV kernel with different input sizes. The SecNDP does not perform well when the amount of public data is significantly large. To overcome these limitations, we propose a novel secure computation framework that leverages multi-party compu￾tation (MPC) to securely offload both linear and nonlinear computations to untrusted PIM hardware. A… view at source ↗
Figure 3
Figure 3. Proposed threat model. TEE is the trusted party, and [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figures from the paper (15 more)
Figure 4
Figure 4. Figure 4: Overview of the UPMEM Architecture. The DPU chip incorporates two essential on-chip mem￾ory elements, namely Instruction RAM (IRAM) and Working RAM (WRAM), with the specific purpose of reducing the access time to the Main RAM (MRAM) for the DPUs. The IRAM, a 24 KB memo…
Figure 5
Figure 5. Figure 5: (a) Counter-mode Encryption: Generated One-Time [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 6
Figure 6. Figure 6: The computation flow of the runtime approach begins with the initiation of a GEMV kernel by the PIM system on the ciphertext. Concurrently, on the CPU side, a set of OTPs is generated, and GEMV computation is performed on them. Finally, the partial results are merged w…
Figure 7
Figure 7. Figure 7: (a) In runtime-based MPC, the CPU generates OTPs and performs GEMV computations, which can cre￾ate bottlenecks on the CPU side. (b) In precomputation-based MPC, these computationally intensive tasks are handled of￾fline, removing them from the critical path and resulti…
Figure 8
Figure 8. Figure 8: Precomputed partial results (resCPU) are securely stored in memory. During runtime, the PIM accelerator per￾forms computations over the ciphertext (Ci). However, the computation on the CPU is limited to decrypting the precom￾puted results (resCPU). 5.3.2 Secure outsour…
Figure 9
Figure 9. Figure 9: (a) Securely outsourcing the linear computation to [PITH_FULL_IMAGE:figures/full_fig_p008_9.png]
Figure 11
Figure 11. Figure 11: (a) CPU-Secure: TEE-based computation on the CPU. The TEE decrypts the encrypted data, enabling it to carry out the required computations. (b) PIM-Insecure: The PIM accelerator directly performs computation on the plain￾text. (c) PIM-Enc/Dec: The PIM accelerator first…
Figure 12
Figure 12. Figure 12: An example of how precomputation can be used for [PITH_FULL_IMAGE:figures/full_fig_p009_12.png]
Figure 13
Figure 13. Figure 13: (Left) Comparing precomputation vs. runtime scheme for MLP. (Right) Online vs. offline proportion in precomputation scheme for MLP. MLP performance analysis [PITH_FULL_IMAGE:figures/full_fig_p011_13.png]
Figure 14
Figure 14. Figure 14: Comparing different MLP implementations: (a) with varying model sizes for a batch size of 64, where increasing the model size enables UPMEM-Precomputation to achieve greater speedups over CPU-Secure. (b) with varying batch sizes for a model size of 20 KB/100 MB per la…
Figure 15
Figure 15. Figure 15: Execution time comparison of different implementations of Embedding Lookup (a) with different embedding table sizes for a batch size of 128, where for larger model sizes, UPMEM-Precomputation can achieve a higher speedup compared to CPU-Secure. (b) with different batc…
Figure 16
Figure 16. Figure 16: Comparing different implementations of logis￾tic regression when having different numbers of samples. UPMEM-Runtime-A(2Y) can achieve higher speedup over CPU-Secure by increasing the number of samples. The UPMEM-Insecure baseline has different implementa￾tions for the…
Figure 18
Figure 18. Figure 18: Comparing different linear regression training im￾plementations with different numbers of samples. By increas￾ing the number of samples, UPMEM-Runtime can achieve higher performance compared to CPU-Secure. Unlike in previous applications, UPMEM-Enc/Dec-V per￾forms bet…
Figure 17
Figure 17. Figure 17: Comparison of homomorphic-based and MPC￾based implementations of linear regression with varying num￾bers of samples. Our MPC-based approach consistently out￾performs the HE-based method. As illustrated in [PITH_FULL_IMAGE:figures/full_fig_p013_17.png]
Figure 19
Figure 19. Figure 19: (a) Unrolling the matrix for performing 2×2 con￾volution with stride = 2. (b) Performing GEMM on DPUs using GEMV kernel. 9 Conclusions Processing-in-Memory is an approach to address the perfor￾mance limitations caused by memory wall constraints. How￾ever, off-chip mem…

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Pith tools

Reviewed August 10, 2026 · model on record in the stance chip above.