Paper Citation Record · LEDGER

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs

As of 9 August 2026, this Paper Citation Record lists 44 of 44 outbound references and 0 inbound Pith citation observations for arXiv:2509.03846.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2509.03846 v1

Coverage vector

measured 44 of 44 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-05T10:41:48.154485Z

measured 44 of 44 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-09T06:31:02.800959+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

44 of 44 outbound references displayed

verified exact10
verified fuzzy8
unresolved12
parse uncertain0
malformed identifier1
metadata mismatch13

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation a27ed251-d192-48b3-9e25-2af6eb3a8929 · outbound

This paper cites Eyeriss: An Energy -Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Eyeriss: An Energy -Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks,

Reference 1

Resolution: metadata mismatch; raw_fallback, observed 2026-08-05T10:41:50.160860Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation b99e6622-812a-496e-8052-7b2ef272e205 · outbound

This paper cites an unresolved cited work.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Unresolved cited work

Reference 2

Resolution: unresolved; no resolver link, observed 2026-08-05T10:41:47.954285Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 3795db01-32ea-4d1e-97d5-d4d6f798bfbf · outbound

This paper cites DianNao,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs DianNao,

Reference 3

Resolution: metadata mismatch; raw_fallback, observed 2026-08-05T10:41:50.030659Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation ddf9a082-c4ee-4270-a649-4cb53e983c69 · outbound

This paper cites Then, IF#2-IF#4 inject Col3, Col4, and Col5 for channels {0, 1}; overlapping columns are forwarded laterally (blue arrows), so only the new column is fetched each time.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Then, IF#2-IF#4 inject Col3, Col4, and Col5 for channels {0, 1}; overlapping columns are forwarded laterally (blue arrows), so only the new column is fetched each time

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T10:41:50.222495Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation d082c75a-df4d-4ad3-8d2d-fad0f03a4781 · outbound

This paper cites Immediately after programming , A_MULS compute messages are multicast to all C-0 SiteOs (entry 2), each carrying an image data and the convolution-pattern bits.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Immediately after programming , A_MULS compute messages are multicast to all C-0 SiteOs (entry 2), each carrying an image data and the convolution-pattern bits

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T10:41:50.231103Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 89ad4f8d-bc06-4b45-bdaf-f1b9d1f96790 · outbound

This paper cites DaDianNao: A Machine-Learning Supercomputer,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs DaDianNao: A Machine-Learning Supercomputer,

Reference 6

Resolution: verified exact; doi, observed 2026-08-05T10:41:48.231939Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 73e050b1-887a-4893-8b53-b1161eb3da91 · outbound

This paper cites ShiDianNao,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs ShiDianNao,

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-05T10:41:47.963204Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 72791949-c036-4369-ad7f-ba021d3a387b · outbound

This paper cites Krishna, H.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Krishna, H

Reference 8

Resolution: malformed identifier; no resolver link, observed 2026-08-05T10:41:47.966033Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e8c25488-160c-4d4a-b9ee-601239398cc3 · outbound

This paper cites an unresolved cited work.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Unresolved cited work

Reference 9

Resolution: unresolved; no resolver link, observed 2026-08-05T10:41:47.969018Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation cd50083c-1b54-4cea-b595-55a745b0e960 · outbound

This paper cites An Evaluation of Edge TPU Accelerators for Convolutional Neural Networks,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs An Evaluation of Edge TPU Accelerators for Convolutional Neural Networks,

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-05T10:41:47.971582Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 6a13fb2d-8af9-42df-8398-cc087920c7de · outbound

This paper cites Custom AI Streaming Accelerator Architecture,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Custom AI Streaming Accelerator Architecture,

Reference 11

Resolution: verified exact; raw_fallback, observed 2026-08-05T10:41:49.806129Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation ad27476a-087d-4cf4-8f52-8db79a6445e6 · outbound

This paper cites Optimizing Off-Chip Memory Access for Deep Neural Network Accelerator,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Optimizing Off-Chip Memory Access for Deep Neural Network Accelerator,

Reference 12

Resolution: metadata mismatch; raw_fallback, observed 2026-08-05T10:41:49.736767Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 568d3761-a98c-4ebe-9f62-7ada2dc6b80f · outbound

This paper cites Minimizing Off-Chip Memory Access for CNN Accelerators,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Minimizing Off-Chip Memory Access for CNN Accelerators,

Reference 13

Resolution: metadata mismatch; raw_fallback, observed 2026-08-05T10:41:49.649827Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 7a827fbd-f43f-4166-817c-681225509249 · outbound

This paper cites EGCN: An Efficient GCN Accelerator for Minimizing Off-Chip Memory Access,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs EGCN: An Efficient GCN Accelerator for Minimizing Off-Chip Memory Access,

Reference 14

Resolution: metadata mismatch; raw_fallback, observed 2026-08-05T10:41:49.590695Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 02b3d286-9795-4519-917d-b8f839544119 · outbound

This paper cites AI and Memory Wall,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs AI and Memory Wall,

Reference 15

Resolution: metadata mismatch; raw_fallback, observed 2026-08-05T10:41:49.531739Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 3982b6cb-ec68-45e4-8612-2eaf89dda641 · outbound

This paper cites Hitting the memory wall,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Hitting the memory wall,

Reference 16

Resolution: metadata mismatch; raw_fallback, observed 2026-08-05T10:41:49.462860Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 717d35c8-a491-448f-9dc7-945bd74e8282 · outbound

This paper cites Occam: Optimal Data Reuse for Convolutional Neural Networks,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Occam: Optimal Data Reuse for Convolutional Neural Networks,

Reference 17

Resolution: verified exact; doi, observed 2026-08-05T10:41:48.210400Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation cbfc19a5-9c0e-478e-864d-1c5eb4d672e8 · outbound

This paper cites Continuous Convolution Accelerator with Data Reuse based on Systolic Architecture,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Continuous Convolution Accelerator with Data Reuse based on Systolic Architecture,

Reference 18

Resolution: verified exact; raw_fallback, observed 2026-08-05T10:41:49.386857Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 1dd39fad-d443-4871-8f54-b08aae2047af · outbound

This paper cites MAESTRO: A Data - Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs MAESTRO: A Data - Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings,

Reference 19

Resolution: unresolved; no resolver link, observed 2026-08-05T10:41:47.994973Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 77644b56-bb7d-4830-80d9-fa4a84a9e152 · outbound

This paper cites A Survey of Coarse -Grained Reconfigurable Architecture and Design,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs A Survey of Coarse -Grained Reconfigurable Architecture and Design,

Reference 20

Resolution: unresolved; no resolver link, observed 2026-08-05T10:41:47.997432Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation dd1d01c0-0b2b-42f3-823d-1c2d506e2d41 · outbound

This paper cites A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective,

Reference 21

Resolution: metadata mismatch; raw_fallback, observed 2026-08-05T10:41:49.257674Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 26e7a0f5-4a73-4d4e-8c2c-acc0a725b0c0 · outbound

This paper cites Karunaratne, A.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Karunaratne, A

Reference 22

Resolution: metadata mismatch; raw_fallback, observed 2026-08-05T10:41:49.188335Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation f65f397c-b1cd-4066-8079-fd20cc65bbf3 · outbound

This paper cites Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC -V SoC on FireSim,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC -V SoC on FireSim,

Reference 23

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T10:41:50.214035Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation ba31cfb3-510c-4b75-9e88-99afaf3fad0c · outbound

This paper cites Timeloop: A Systematic Approach to DNN Accelerator Evaluation,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Timeloop: A Systematic Approach to DNN Accelerator Evaluation,

Reference 24

Resolution: unresolved; no resolver link, observed 2026-08-05T10:41:48.113608Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 55a9cca8-c6a9-40c8-bb5c-ad4fd82739b2 · outbound

This paper cites an unresolved cited work.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Unresolved cited work

Reference 25

Resolution: verified exact; raw_fallback, observed 2026-08-05T10:41:49.130455Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation e7fc50e6-3e26-4106-81d3-01b2c9fa3bcf · outbound

This paper cites Ultra-Elastic CGRAs for Irregular Loop Specialization,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Ultra-Elastic CGRAs for Irregular Loop Specialization,

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T10:41:50.205233Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 4cd6b98b-4c55-43af-962f-477f5d324b2e · outbound

This paper cites DRESC: a retargetable compiler for coarse -grained reconfigurable architectures,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs DRESC: a retargetable compiler for coarse -grained reconfigurable architectures,

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T10:41:50.196857Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 363d3827-c321-4fa6-a92e-2a1ab11925fb · outbound

This paper cites Scratchpad Memory Management for Deep Learning Accelerators,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Scratchpad Memory Management for Deep Learning Accelerators,

Reference 28

Resolution: unresolved; no resolver link, observed 2026-08-05T10:41:48.124723Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 34c8d506-496b-4393-8207-28a5fc82200f · outbound

This paper cites Deep Learning Model Compression With Rank Reduction in Tensor Decomposition,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Deep Learning Model Compression With Rank Reduction in Tensor Decomposition,

Reference 29

Resolution: metadata mismatch; raw_fallback, observed 2026-08-05T10:41:48.727904Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 23928a7e-49e8-4683-9996-e018d379f360 · outbound

This paper cites Design of a Convolutional Neural Network Accelerator Based on On -Chip Data Reordering,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Design of a Convolutional Neural Network Accelerator Based on On -Chip Data Reordering,

Reference 30

Resolution: verified exact; doi, observed 2026-08-05T10:41:48.193916Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 403d12c0-03d0-4b32-8fb2-43a85f732243 · outbound

This paper cites Twenty Years of Automated Methods for Mapping Applications on CGRA,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Twenty Years of Automated Methods for Mapping Applications on CGRA,

Reference 31

Resolution: unresolved; no resolver link, observed 2026-08-05T10:41:48.119448Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 6fe51777-82cd-40b7-bd90-2ad7127a32a5 · outbound

This paper cites Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes,

Reference 32

Resolution: metadata mismatch; raw_fallback, observed 2026-08-05T10:41:48.875883Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 5930f307-3779-43fb-a953-cfd7913f3736 · outbound

This paper cites Evaluating Modern GPU Interconnect: PCIe, NVLink, NV-SLI, NVSwitch and GPUDirect,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Evaluating Modern GPU Interconnect: PCIe, NVLink, NV-SLI, NVSwitch and GPUDirect,

Reference 33

Resolution: metadata mismatch; raw_fallback, observed 2026-08-05T10:41:48.529776Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation c4ef69ad-5822-406c-ba86-44ac324d4536 · outbound

This paper cites Accelerating PageRank Algorithmic Tasks with a new Programmable Hardware Architecture,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Accelerating PageRank Algorithmic Tasks with a new Programmable Hardware Architecture,

Reference 34

Resolution: unresolved; no resolver link, observed 2026-08-05T10:41:48.140552Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 56c757d4-72b3-4db2-be69-81d5af935602 · outbound

This paper cites Loom: Exploiting Weight and Activation Precisions to Accelerate Convolutional Neural Networks,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Loom: Exploiting Weight and Activation Precisions to Accelerate Convolutional Neural Networks,

Reference 35

Resolution: metadata mismatch; raw_fallback, observed 2026-08-05T10:41:48.667214Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 705e71ed-78a6-49c9-9993-1a878bf66a31 · outbound

This paper cites Greedy Prefetch for Reducing Off -Chip Memory Accesses in Convolutional Neural Network Inference,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Greedy Prefetch for Reducing Off -Chip Memory Accesses in Convolutional Neural Network Inference,

Reference 36

Resolution: verified exact; doi, observed 2026-08-05T10:41:48.184636Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation f3345a10-8cb3-431d-a98f-3baf08e2c925 · outbound

This paper cites Present and Future, Challenges of High Bandwith Memory (HBM),.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Present and Future, Challenges of High Bandwith Memory (HBM),

Reference 37

Resolution: verified exact; raw_fallback, observed 2026-08-05T10:41:48.605060Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 79fc0e44-6f13-4c9d-b52b-93c107f706cb · outbound

This paper cites The Evolution of the PCI Express (PCIe) Specification: In its Sixth Generation, Third Decade and Still Going Strong,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs The Evolution of the PCI Express (PCIe) Specification: In its Sixth Generation, Third Decade and Still Going Strong,

Reference 38

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T10:41:50.179470Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation ecda4eb8-65c8-48f1-8f13-300a45af120f · outbound

This paper cites Diversification of DRAM Application and Memory Hierarchy,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Diversification of DRAM Application and Memory Hierarchy,

Reference 39

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T10:41:50.171102Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 705315b3-ee16-4bff-b8c4-6ad3e60d75a0 · outbound

This paper cites Messaging-based Intelligent Processing Unit (m- IPU) for next generation AI computing,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Messaging-based Intelligent Processing Unit (m- IPU) for next generation AI computing,

Reference 40

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T10:41:50.188189Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 9b97d095-68d7-4cd9-9bca-ceadc31e25f3 · outbound

This paper cites Implications of memory embedding and hierarchy on the performance of MAVeC AI accelerators,.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Implications of memory embedding and hierarchy on the performance of MAVeC AI accelerators,

Reference 41

Resolution: unresolved; no resolver link, observed 2026-08-05T10:41:48.145663Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 2b268739-5596-4af4-bd79-55dfedc6b3a4 · outbound

This paper cites Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators

Reference 42

Resolution: verified exact; local_arxiv, observed 2026-08-05T10:41:48.244595Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation bbc92045-163d-4888-9653-76ec7d45c066 · outbound

This paper cites an unresolved cited work.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Unresolved cited work

Reference 425

Resolution: unresolved; no resolver link, observed 2026-08-05T10:41:48.012541Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation d1aef5bf-c274-4820-970c-9c723711391d · outbound

This paper cites Hierarchical Memory Decoding for Video Captioning.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Hierarchical Memory Decoding for Video Captioning

Reference 2002

Resolution: verified exact; local_arxiv, observed 2026-08-05T10:41:49.005490Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Pith citing papers

No inbound Pith citation observations are available.