Paper Citation Record · LEDGER

Pattern-Guided Design Space Exploration for FPGA Accelerator Design

As of 18 August 2026, this Paper Citation Record lists 36 of 36 outbound references and 0 inbound Pith citation observations for arXiv:2607.15068.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2607.15068 v1

Coverage vector

measured 36 of 36 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-02T00:17:24.756369Z

measured 36 of 36 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-17T06:30:58.91139+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

36 of 36 outbound references displayed

verified exact0
verified fuzzy0
unresolved36
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 378ffafd-f606-491b-9152-69f8ff9fb3bd · outbound

This paper cites Stiff circuit system modeling via transformer,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design Stiff circuit system modeling via transformer,

Reference 1

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.616455Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 6a1f8dce-96c4-4a08-8b77-9ce773d9c3c6 · outbound

This paper cites Labeling cost sensitive batch active learning for brain tumor segmentation,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design Labeling cost sensitive batch active learning for brain tumor segmentation,

Reference 2

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.621210Z

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Observation a962b6c3-a879-48c5-a3d9-7e34f7c2cf94 · outbound

This paper cites Patternpaint: Practical layout pattern generation using diffusion-based inpainting,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design Patternpaint: Practical layout pattern generation using diffusion-based inpainting,

Reference 3

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.625215Z

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Unavailable: canonical work link unavailable.

Observation 4f917b3a-372b-4185-b296-1ac825b77bb3 · outbound

This paper cites Diffusion- model-enhanced layout pattern generation for sub-3nm dfm,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design Diffusion- model-enhanced layout pattern generation for sub-3nm dfm,

Reference 4

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.629526Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f028c881-6169-40cf-8cb0-92941eb52ae8 · outbound

This paper cites Dark silicon and the end of multicore scaling,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design Dark silicon and the end of multicore scaling,

Reference 5

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.634349Z

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Observation 9c61af0a-1f87-48f3-924a-e4c306ced814 · outbound

This paper cites A reconfigurable fabric for accelerating large-scale datacenter services,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design A reconfigurable fabric for accelerating large-scale datacenter services,

Reference 6

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.638519Z

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Observation 198c0bc9-ac30-4cd7-9d60-9c1cd76e7863 · outbound

This paper cites A cloud-scale acceleration architecture,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design A cloud-scale acceleration architecture,

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.643148Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 0d8db604-7992-42cf-87ab-969635bb4d95 · outbound

This paper cites FPGA HLS today: Successes, challenges, and opportunities,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design FPGA HLS today: Successes, challenges, and opportunities,

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.647108Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation cc300a7b-0064-4c30-9236-12db74c7eabb · outbound

This paper cites High-level synthesis design space explo- ration: Past, present, and future,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design High-level synthesis design space explo- ration: Past, present, and future,

Reference 9

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.651663Z

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Unavailable: canonical work link unavailable.

Observation d22894bf-4280-43bd-814f-0bf2401e0285 · outbound

This paper cites Allo: A programming model for composable accelerator design,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design Allo: A programming model for composable accelerator design,

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.655707Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ca7a63a8-de96-4bdc-a64e-515179bf83bb · outbound

This paper cites The landscape of parallel computing research: A view from Berkeley,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design The landscape of parallel computing research: A view from Berkeley,

Reference 11

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.659883Z

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Unavailable: canonical work link unavailable.

Observation ec6b33dd-5bde-49a7-a937-88bb6f6c3be6 · outbound

This paper cites MachSuite: Benchmarks for accelerator design and customized architectures,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design MachSuite: Benchmarks for accelerator design and customized architectures,

Reference 12

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.663798Z

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Observation 17460494-0aa9-4f0a-bbfd-a5bcfd233868 · outbound

This paper cites Rodinia: A benchmark suite for heterogeneous computing,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design Rodinia: A benchmark suite for heterogeneous computing,

Reference 13

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.668133Z

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Observation 1f609b53-e036-4c72-b597-a09a417ac139 · outbound

This paper cites CHStone: A benchmark program suite for practical C-based high-level synthesis,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design CHStone: A benchmark program suite for practical C-based high-level synthesis,

Reference 14

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.671685Z

Source-reported events for the cited work

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Observation 718b57ff-d4b4-4c6e-a00b-83f8d4addd0e · outbound

This paper cites Rosetta: A realistic high-level synthesis benchmark suite for software programmable FPGAs,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design Rosetta: A realistic high-level synthesis benchmark suite for software programmable FPGAs,

Reference 15

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.675682Z

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Observation a85f4013-f31a-4eb6-a41c-3bcd1b77acb1 · outbound

This paper cites MLPerf inference benchmark,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design MLPerf inference benchmark,

Reference 16

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.679406Z

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Observation 09740543-f3bb-45af-8e2d-60b5146bbdc0 · outbound

This paper cites ScaleHLS: A scalable high-level synthesis framework with multi-level transforma- tions and optimizations,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design ScaleHLS: A scalable high-level synthesis framework with multi-level transforma- tions and optimizations,

Reference 17

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.683062Z

Source-reported events for the cited work

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Observation 191058f6-bdd5-4ffb-a1e0-1216521ae684 · outbound

This paper cites Decoupling algorithms from schedules for easy optimization of image processing pipelines,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design Decoupling algorithms from schedules for easy optimization of image processing pipelines,

Reference 18

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.686860Z

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Unavailable: canonical work link unavailable.

Observation 25602d2a-73f3-4e92-8cf1-5c7a0ca62f6e · outbound

This paper cites TVM: An automated end-to-end optimizing compiler for deep learning,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design TVM: An automated end-to-end optimizing compiler for deep learning,

Reference 19

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.690537Z

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Observation 0b5850d9-3e51-48c6-b583-5b4d2de8a59d · outbound

This paper cites HeteroCL: A multi-paradigm programming infrastructure for software-defined reconfigurable computing,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design HeteroCL: A multi-paradigm programming infrastructure for software-defined reconfigurable computing,

Reference 20

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.694110Z

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Observation 9c80d0d9-ad0d-462a-b72e-56f4e0c8b7d3 · outbound

This paper cites fpgaConvNet: A framework for mapping convolutional neural networks on FPGAs,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design fpgaConvNet: A framework for mapping convolutional neural networks on FPGAs,

Reference 21

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.698711Z

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Observation fb874a9a-35d3-4976-887a-a12f40051b41 · outbound

This paper cites DNNBuilder: An automated tool for building high-performance DNN hardware accelerators for FPGAs,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design DNNBuilder: An automated tool for building high-performance DNN hardware accelerators for FPGAs,

Reference 22

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.702515Z

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Observation fa761949-cffc-4757-adc7-416213ccc13c · outbound

This paper cites In-datacenter performance analysis of a tensor processing unit,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design In-datacenter performance analysis of a tensor processing unit,

Reference 23

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.706434Z

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Unavailable: canonical work link unavailable.

Observation d1c38035-6d82-4be7-9b27-f0fb37943058 · outbound

This paper cites Gemmini: Enabling systematic deep-learning archi- tecture evaluation via full-stack integration,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design Gemmini: Enabling systematic deep-learning archi- tecture evaluation via full-stack integration,

Reference 24

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.710251Z

Source-reported events for the cited work

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Observation 684f6316-c0d1-4eb0-a77e-246ed03778c9 · outbound

This paper cites LegUp: High-level synthesis for FPGA-based processor/accelerator systems,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design LegUp: High-level synthesis for FPGA-based processor/accelerator systems,

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.713826Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 30668b16-dfad-42ab-807e-c86f460a439f · outbound

This paper cites MLIR: A Compiler Infrastructure for the End of Moore's Law.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design MLIR: A Compiler Infrastructure for the End of Moore's Law

Reference 26

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.717495Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 9161ff0c-ee36-468c-9fd3-9efaa229c068 · outbound

This paper cites VTR 7.0: Next generation architecture and CAD system for FPGAs,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design VTR 7.0: Next generation architecture and CAD system for FPGAs,

Reference 27

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.721376Z

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Observation ac3d45c8-9819-425b-bba7-45e074e48eeb · outbound

This paper cites AutoBridge: Coupling coarse-grained floorplanning and pipelining for high-frequency HLS design on multi-die FPGAs,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design AutoBridge: Coupling coarse-grained floorplanning and pipelining for high-frequency HLS design on multi-die FPGAs,

Reference 28

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.725168Z

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Observation 1aff14d2-78fd-4a3a-b581-6af46fcee82c · outbound

This paper cites TAPA: A scalable task-parallel dataflow programming framework for modern FPGAs with co-optimization of HLS and physical design,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design TAPA: A scalable task-parallel dataflow programming framework for modern FPGAs with co-optimization of HLS and physical design,

Reference 29

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.729014Z

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Observation 40d5d297-2483-4f1c-9fb9-6833534d845f · outbound

This paper cites Chisel: Constructing hardware in a Scala embedded language,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design Chisel: Constructing hardware in a Scala embedded language,

Reference 30

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.732720Z

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Unavailable: canonical work link unavailable.

Observation 7b91fdbf-250c-48ee-babb-99e60df2bef4 · outbound

This paper cites OpenROAD: Toward a self-driving, open-source digital layout implementation tool chain,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design OpenROAD: Toward a self-driving, open-source digital layout implementation tool chain,

Reference 31

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.736677Z

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Observation 61314dd7-229e-4dfc-af6a-95794cd5bfe5 · outbound

This paper cites On learning-based methods for design- space exploration with high-level synthesis,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design On learning-based methods for design- space exploration with high-level synthesis,

Reference 32

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.740448Z

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Unavailable: canonical work link unavailable.

Observation 0cbee2a1-e13c-4a78-8439-42d9a813cc79 · outbound

This paper cites AutoDSE: Enabling software programmers to design efficient FPGA accelerators,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design AutoDSE: Enabling software programmers to design efficient FPGA accelerators,

Reference 33

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.744196Z

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Unavailable: canonical work link unavailable.

Observation 4245a5a1-9cab-4597-bf05-4f159bb1d820 · outbound

This paper cites From predict to generate: A cross-layer survey of generative ai for ic design and manufacturing,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design From predict to generate: A cross-layer survey of generative ai for ic design and manufacturing,

Reference 34

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.747896Z

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Observation a5db22e7-d50b-4321-88ee-39af16fe3e46 · outbound

This paper cites Toward engineering agi: Benchmarking the engineering design capabilities of llms,.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design Toward engineering agi: Benchmarking the engineering design capabilities of llms,

Reference 35

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.752237Z

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Observation 202d4c09-bd87-4c62-b668-f24875144dc3 · outbound

This paper cites Available: https://proceedings.neurips.cc/paper files/ paper/2025/file/664f777548205fb6e0cbb0965e8d2e16-Paper-Datasets and Benchmarks Track.pdf.

Pattern-Guided Design Space Exploration for FPGA Accelerator Design Available: https://proceedings.neurips.cc/paper files/ paper/2025/file/664f777548205fb6e0cbb0965e8d2e16-Paper-Datasets and Benchmarks Track.pdf

Reference 2025

Resolution: unresolved; no resolver link, observed 2026-08-02T00:17:24.756369Z

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Pith citing papers

No inbound Pith citation observations are available.