Paper Citation Record · LEDGER

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper

As of 11 August 2026, this Paper Citation Record lists 47 of 47 outbound references and 0 inbound Pith citation observations for arXiv:2507.10912.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2507.10912 v1

Coverage vector

measured 47 of 47 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-06T17:29:23.450957Z

measured 47 of 47 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-11T06:34:44.6726+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

47 of 47 outbound references displayed

verified exact1
verified fuzzy43
unresolved3
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 1939a70d-f63b-4736-b26b-423614030306 · outbound

This paper cites On area/depth trade-off in lut-based fpga technology mapping.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper On area/depth trade-off in lut-based fpga technology mapping

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:31.146725Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 9e03c8b3-9cfd-4be2-8cf7-b19388b38073 · outbound

This paper cites Flowmap: An optimal technology mapping algorithm for delay optimization in lookup-table based fpga designs.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Flowmap: An optimal technology mapping algorithm for delay optimization in lookup-table based fpga designs

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:30.965684Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 69bbc5a7-567f-4b35-a64c-e3d6cf499cd9 · outbound

This paper cites Complexity of the lookup- table minimization problem for fpga technology mapping.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Complexity of the lookup- table minimization problem for fpga technology mapping

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:30.801447Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation dd61b009-a761-4cbc-916c-739d784973d5 · outbound

This paper cites Low-power technology mapping for fpga architectures with dual supply voltages.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Low-power technology mapping for fpga architectures with dual supply voltages

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:30.652778Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 913ee486-5363-4286-b23d-249695177031 · outbound

This paper cites Improvements to technology mapping for lut-based fpgas.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Improvements to technology mapping for lut-based fpgas

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:30.479999Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation e5245bf6-8d04-402b-ac97-8d0f2a86c419 · outbound

This paper cites Fpga technology mapping: a study of optimality.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Fpga technology mapping: a study of optimality

Reference 6

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:30.320956Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 3e524b64-5665-41a1-b495-0b8731f655ae · outbound

This paper cites Technology mapping for fpgas with embedded memory blocks.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Technology mapping for fpgas with embedded memory blocks

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:30.201501Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 150c0207-4195-4be9-83f4-d30397d3dd36 · outbound

This paper cites Combinational profiles of sequential benchmark circuits.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Combinational profiles of sequential benchmark circuits

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:30.004288Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 9dd812f1-0f19-489f-a34c-9c50a4720cc7 · outbound

This paper cites VTR 8.0: Next generation architecture and CAD system for FPGAs.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper VTR 8.0: Next generation architecture and CAD system for FPGAs

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:29.881732Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 1694d0d3-c9b1-49d4-be20-05eebe20e94d · outbound

This paper cites The EPFL Logic Synthesis Libraries.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper The EPFL Logic Synthesis Libraries

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-06T17:29:20.390547Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation fe68fb81-cf1f-47dc-bfc3-5d34c305785f · outbound

This paper cites Tree-based mapping of algorithms to predefined structures.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Tree-based mapping of algorithms to predefined structures

Reference 11

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:29.678784Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 5e8d32e9-2547-463e-bb49-3fc00aa41078 · outbound

This paper cites Technology Mapping with Boolean Matching, Supergates and Choices.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Technology Mapping with Boolean Matching, Supergates and Choices

Reference 12

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:29.406375Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation e8884f14-65f4-4ffd-ab60-8e4d404dee4a · outbound

This paper cites an unresolved cited work.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Unresolved cited work

Reference 13

Resolution: unresolved; raw_fallback, observed 2026-08-06T17:29:29.206712Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 2665931f-2cc1-4a6a-a94a-8a6344c34ce5 · outbound

This paper cites Read your circuit: leveraging word embedding to guide logic optimization.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Read your circuit: leveraging word embedding to guide logic optimization

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:28.996338Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation e6748fdb-6f1b-4146-ac54-0b59ca3fb0e9 · outbound

This paper cites Boolgebra: Attributed graph-learning for boolean algebraic manipulation.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Boolgebra: Attributed graph-learning for boolean algebraic manipulation

Reference 15

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:28.672547Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation dcc950c0-e994-4ddf-bca0-f2d8e454029a · outbound

This paper cites Slap: A supervised learning approach for priority cuts technology mapping.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Slap: A supervised learning approach for priority cuts technology mapping

Reference 16

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:28.325656Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 932fd7bf-bec6-4388-824c-822274121bbd · outbound

This paper cites Nvcell: Standard cell layout in advanced technology nodes with reinforcement learning.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Nvcell: Standard cell layout in advanced technology nodes with reinforcement learning

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:28.039390Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 41e9bd08-18d6-4959-be96-f2538cbecc9f · outbound

This paper cites InTime: A Machine Learning Approach for Efficient Selection of FPGA CAD Tool Parameters.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper InTime: A Machine Learning Approach for Efficient Selection of FPGA CAD Tool Parameters

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:27.791191Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation bcc9dcea-a6e8-4300-b2fd-bd82dbf5304b · outbound

This paper cites LAMDA: Learning-Assisted Multi-stage Autotuning for FPGA Design Closure.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper LAMDA: Learning-Assisted Multi-stage Autotuning for FPGA Design Closure

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:27.601743Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 234c5fec-d71e-478d-af4f-32516a4e41eb · outbound

This paper cites Ziegler, Ramon Bertran Monfort, Alper Buyuktosunoglu, and Pradip Bose.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Ziegler, Ramon Bertran Monfort, Alper Buyuktosunoglu, and Pradip Bose

Reference 20

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:27.345245Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation f5c86be2-555a-4532-9db5-42659fb910d4 · outbound

This paper cites Developing synthesis flows without human knowledge.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Developing synthesis flows without human knowledge

Reference 21

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:27.047159Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 7f409294-fa99-4545-b0eb-bfe91717e36d · outbound

This paper cites DRiLLS: Deep Reinforcement Learning for Logic Synthesis.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper DRiLLS: Deep Reinforcement Learning for Logic Synthesis

Reference 22

Resolution: verified exact; local_arxiv, observed 2026-08-06T17:29:23.608137Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation e1563105-750a-4c3e-bb50-5f259ca8768c · outbound

This paper cites High performance graph convolutional networks with applications in testability analysis.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper High performance graph convolutional networks with applications in testability analysis

Reference 23

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:26.852533Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 71e8e469-9c3a-42ec-91f1-499e13bf0a67 · outbound

This paper cites Decision making in synthesis cross technologies using lstms and transfer learning.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Decision making in synthesis cross technologies using lstms and transfer learning

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:26.667138Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 30c89e53-b179-49a6-be36-574da6804522 · outbound

This paper cites Flowtune: Practical multi-armed bandits in boolean optimiza- tion.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Flowtune: Practical multi-armed bandits in boolean optimiza- tion

Reference 25

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:26.497088Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation b6226b70-40c4-45fb-bb85-0fd7004acd1d · outbound

This paper cites Flowtune: End-to-end automatic logic optimization exploration via domain-specific multi-armed bandit.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Flowtune: End-to-end automatic logic optimization exploration via domain-specific multi-armed bandit

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:26.363226Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 716116d7-29d6-4e87-92f1-8e876206f430 · outbound

This paper cites Machine learning for agile fpga design.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Machine learning for agile fpga design

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:26.230717Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 0eb4d4ad-afa0-4312-9c3e-ff3ffeddf702 · outbound

This paper cites Efficient Design Space Exploration via Statistical Sampling and AdaBoost Learning.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Efficient Design Space Exploration via Statistical Sampling and AdaBoost Learning

Reference 28

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:26.080780Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 8a14c865-7da3-4b85-a728-106714ff7039 · outbound

This paper cites Maptune: Advancing asic technology mapping via reinforcement learning guided library tuning.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Maptune: Advancing asic technology mapping via reinforcement learning guided library tuning

Reference 29

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:25.907700Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation c1b2e3af-3bb9-4b59-98cf-731cb0915847 · outbound

This paper cites Verilog-to- pyg-a framework for graph learning and augmentation on rtl designs.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Verilog-to- pyg-a framework for graph learning and augmentation on rtl designs

Reference 30

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:25.793922Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation dd6fa068-f0eb-44ad-8cb5-787bc2e07e7c · outbound

This paper cites E-syn: E-graph rewriting with technology-aware cost functions for logic synthesis.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper E-syn: E-graph rewriting with technology-aware cost functions for logic synthesis

Reference 31

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:25.695887Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 1adac7fc-d5a4-401c-abdd-5b30f40509f1 · outbound

This paper cites Gamora: Graph learning based symbolic reasoning for large-scale boolean networks.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Gamora: Graph learning based symbolic reasoning for large-scale boolean networks

Reference 32

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:25.529052Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation aaff7ec2-1772-4291-9999-576f2267ea77 · outbound

This paper cites Less is more: Hop-wise graph attention for scalable and generalizable learning on circuits.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Less is more: Hop-wise graph attention for scalable and generalizable learning on circuits

Reference 33

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:25.391900Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 2b6f9199-4a86-4023-b08e-8e390d9fdc31 · outbound

This paper cites Smoothe: Differentiable e-graph extraction.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Smoothe: Differentiable e-graph extraction

Reference 34

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:25.227036Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation fd6bc52f-d686-448d-8117-d3b5eb6e3a75 · outbound

This paper cites Differ- entiable combinatorial scheduling at scale.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Differ- entiable combinatorial scheduling at scale

Reference 35

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:25.102872Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 11e90544-651c-4ae4-ada4-a56d929c5e51 · outbound

This paper cites Respect: Reinforcement learning based edge scheduling on pipelined coral edge tpus.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Respect: Reinforcement learning based edge scheduling on pipelined coral edge tpus

Reference 36

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:24.981940Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 8ff4ae6e-b525-4da9-9fd4-84ac38915ce3 · outbound

This paper cites Accelerating exact combinatorial optimization via rl-based initialization-a case study in scheduling.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Accelerating exact combinatorial optimization via rl-based initialization-a case study in scheduling

Reference 37

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:24.828343Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation fd1e889d-1eff-4cb7-bcd1-b3d9995b9074 · outbound

This paper cites Cbtune: Contextual bandit tuning for logic synthesis.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Cbtune: Contextual bandit tuning for logic synthesis

Reference 38

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:24.716604Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 4ec30de5-fef9-4db7-9303-323f862caa95 · outbound

This paper cites Abc: A system for sequential synthesis and verification.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Abc: A system for sequential synthesis and verification

Reference 39

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:24.608037Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 8c48e92f-c28c-4108-8478-da3a1a33bf38 · outbound

This paper cites ABC: An Academic Industrial- strength Verification tool.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper ABC: An Academic Industrial- strength Verification tool

Reference 40

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:24.495065Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 61a15b9f-e8fa-4c0a-8502-05b314ae11b9 · outbound

This paper cites Painting on placement: Forecasting routing congestion using conditional generative adversarial nets.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Painting on placement: Forecasting routing congestion using conditional generative adversarial nets

Reference 41

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:24.380471Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation c38d456d-62ee-43ba-9970-295102790bd8 · outbound

This paper cites Fast and accurate estimation of quality of results in high-level synthesis with machine learning.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Fast and accurate estimation of quality of results in high-level synthesis with machine learning

Reference 42

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:24.231371Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 9c7d078b-ed45-43ef-a6ec-16b11c3b3e5f · outbound

This paper cites Robust gnn-based representation learning for hls.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Robust gnn-based representation learning for hls

Reference 43

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:24.131777Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation dcc364e4-b522-4ef3-8f6c-441f48b432c8 · outbound

This paper cites Algorithms for multi-armed bandit problems.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Algorithms for multi-armed bandit problems

Reference 44

Resolution: unresolved; no resolver link, observed 2026-08-06T17:29:23.269942Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 77547202-1c0c-4407-806c-f9d133beab6d · outbound

This paper cites Upper confidence bound based decision making strategies and dynamic spectrum access.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Upper confidence bound based decision making strategies and dynamic spectrum access

Reference 45

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:24.015090Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 0dad2c26-bcae-471e-990e-6a9dec83ee2b · outbound

This paper cites Asap7: A 7-nm finfet predictive process design kit.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper Asap7: A 7-nm finfet predictive process design kit

Reference 46

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:23.894135Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation c028f314-000e-49be-9906-828ee7f55928 · outbound

This paper cites URL https://eda.ncsu.edu/freepdk/freepdk45/.

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper URL https://eda.ncsu.edu/freepdk/freepdk45/

Reference 47

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T17:29:23.766123Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Pith citing papers

No inbound Pith citation observations are available.