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Standalone FPGA-Based QAOA Emulator for Weighted-MaxCut on Embedded Devices

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arxiv 2502.11316 v2 pith:FIO4U2FH submitted 2025-02-16 cs.ET quant-ph

classification cs.ETquant-ph
keywords qaoadevicesembeddedemulatorfpga-basedtimesconfigurationsdesign
verification ladder T0 review T1 audit T2 compute T3 formal
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Quantum computing QC emulation is crucial for advancing QC applications, especially given the scalability constraints of current devices. FPGA-based designs offer an efficient and scalable alternative to traditional large-scale platforms, but most are tightly integrated with high-performance systems, limiting their use in mobile and edge environments. This study introduces a compact, standalone FPGA-based QC emulator designed for embedded systems, leveraging the Quantum Approximate Optimization Algorithm (QAOA) to solve the Weighted-MaxCut problem. By restructuring QAOA operations for hardware compatibility, the proposed design reduces time complexity from O(N^2) to O(N), where N equals 2^n for n qubits. This reduction, coupled with a pipeline architecture, significantly minimizes resource consumption, enabling support for up to nine qubits on mid-tier FPGAs, roughly three times more than comparable designs. Additionally, the emulator achieved energy savings ranging from 1.53 times for two-qubit configurations to up to 852 times for nine-qubit configurations, compared to software-based QAOA on embedded processors. These results highlight the practical scalability and resource efficiency of the proposed design, providing a robust foundation for QC emulation in resource-constrained edge devices.

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Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. HSF-S: Speed-Optimized Compilation and Acceleration for Hybrid Schrodinger-Feynman Quantum Circuit Emulation

    quant-ph 2026-07 conditional novelty 6.5 of 10

    HSF-S reduces HSF effective path cost by up to 90% via rank-aware reordering and discounted-gain SWAP insertion, then accelerates the compiled workloads up to 4.34× on a dedicated RISC-V processor.

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