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Inference with Artificial Neural Networks on Analog Neuromorphic Hardware

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arxiv 2006.13177 v3 pith:GSHYVRNI submitted 2020-06-23 cs.NE

classification cs.NE
keywords analognetworksneuralartificialbrainscales-2circuitsdesigneddigital
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The neuromorphic BrainScaleS-2 ASIC comprises mixed-signal neurons and synapse circuits as well as two versatile digital microprocessors. Primarily designed to emulate spiking neural networks, the system can also operate in a vector-matrix multiplication and accumulation mode for artificial neural networks. Analog multiplication is carried out in the synapse circuits, while the results are accumulated on the neurons' membrane capacitors. Designed as an analog, in-memory computing device, it promises high energy efficiency. Fixed-pattern noise and trial-to-trial variations, however, require the implemented networks to cope with a certain level of perturbations. Further limitations are imposed by the digital resolution of the input values (5 bit), matrix weights (6 bit) and resulting neuron activations (8 bit). In this paper, we discuss BrainScaleS-2 as an analog inference accelerator and present calibration as well as optimization strategies, highlighting the advantages of training with hardware in the loop. Among other benchmarks, we classify the MNIST handwritten digits dataset using a two-dimensional convolution and two dense layers. We reach 98.0% test accuracy, closely matching the performance of the same network evaluated in software.

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  1. Intrinsic-Noise Consolidation: A Doob-Barrier-Conditioned Diffusion Turns Analog Device Noise into a Continual-Learning Resource

    cs.LG 2026-07 conditional novelty 7.0 of 10

    Conditioning per-synapse weight dynamics on a memory-critical barrier via a Doob h-transform turns intrinsic analog device noise into a non-monotonic consolidation resource for continual learning.

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