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REVIEW 3 major objections 5 minor 96 references

Spiking Neural Networks for Inference and Learning: A Memristor-based Design Perspective

T0 review · 3 major / 5 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read This review argues that memristor-based neuromorphic systems should be built around device-aware, gradient-derived three-factor learning rules rather than classical STDP or drop-in memory replacement.

desk verdict A solid review chapter whose original contributions are mostly the authors' earlier results; the pulse-count compensation idea is clear but not robustly validated against the non-idealities it catalogs. read the letter →

arxiv 1909.01771 v2 pith:LATT5EJV submitted 2019-09-04 cs.ET

M. E. Fouda , F. Kurdahi , A. Eltawil , E. Neftci This is my paper · ORCID
classification cs.ET
keywords spikingneuralnetworksmemristorsRRAMthree-factorlearningrulesSTDPneuromorphichardwaresynapticplasticitycrossbararrays
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Memristors have not yet delivered their promised gains for neuromorphic computing, this review argues, because they are typically slotted in as a replacement for conventional memory. The way forward is to choose learning rules that match the physics of the devices: multifactor, gradient-derived plasticity rules with a modulatory third factor, which the review claims outperform classical spike-timing-dependent plasticity. The concrete mechanism is a pulse-count compensation scheme: using an exponential model of RRAM conductance updates, the number of programming pulses is computed so that the actual conductance change equals the desired weight change, compensating for nonlinearity and asymmetry. The result is a design perspective in which device nonidealities such as stochasticity become resources rather than obstacles.

What carries the argument

The load-bearing object is the exponential conductance-update model of Eq. (8), with fitted parameters $G_{\mathrm{max}}, G_{\mathrm{min}}, \alpha_P, \alpha_D, \beta_P, \beta_D$ that capture the asymmetric nonlinearity of RRAM potentiation and depression. Working from this model, the review derives the pulse-count compensation equations (14)-(17) and (23)-(24): for a desired weight change $\Delta G$, the required number of programming pulses is computed from the current conductance $G(n)$ and the device parameters, using logarithms that can be linearized for hardware. Combined with a three-factor learning rule in which the third factor is the modulating signal $M_i$ (error, surprise, or reward), this machinery makes the device's conductance change proportional to the learning rule's weight update, turning a device nonideality into a controlled part of the computation.

What would settle it

Program a batch of RRAMs with the pulse counts computed by Eqs. (23)-(24) while tracking each device's actual conductance after every pulse; if the measured conductance changes deviate from the predicted $\Delta G$ by more than the fitted noise, or if the ICA demixing weights fail to converge to the inverse mixing matrix over $10^4$ samples, the central claim fails. A simpler check is to measure the conductance change after one predicted potentiation pulse starting from $G_{\mathrm{min}}$ and test whether it matches $(G_{\mathrm{max}}-G)(1-e^{-\alpha_P})$.

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Extended reading notes

Core claim

The review's central claim is that the success of memristor-based neuromorphic systems depends on co-designing the learning rule with the device: instead of trying to store weights in RRAM as if it were SRAM, the plasticity rule should be derived from gradient-based optimization of a task objective and expressed as a three-factor rule $\Delta W_{ij}\propto f_{\mathrm{pre}}(S_j) f_{\mathrm{post}}(S_i) M_i$, where the third factor $M_i$ carries task-level error, surprise, or reward. It argues such rules generally achieve higher performance than classical STDP, which lacks the modulation term and is an incomplete description of plasticity. To bridge algorithm and hardware, the review adapts an exponential model of RRAM conductance update, $G(t)=G_{\mathrm{max}}-\beta_P e^{-\alpha_P n}$ for potentiation and $G(t)=G_{\mathrm{min}}+\beta_D e^{-\alpha_D n}$ for depression, and inverts it to compute the number of programming pulses needed to produce a desired change in conductance, so that the device's nonlinear, asymmetric update behaves like the prescribed learning rule. The scheme is demonstrated on a biologically plausible three-factor rule for independent component analysis, where the demixing weights converge toward the inverse of the mixing matrix despite the device's asymmetric nonlinearity and pulse-to-pulse variability.

Load-bearing premise

The pulse-count compensation scheme assumes that the exponential model of Eq. (8), fitted to one Mo/TiOx/TiN device at three programming voltages, describes the real conductance update of every programmed device; if actual RRAM dynamics drift from this exponential form, the claimed exact realization of the learning rule and the ICA convergence no longer follow.

Editorial extensions

If this is right

  • Memristor crossbars should be viewed as computational substrates whose update physics implements the learning rule, not as dense memory blocks: weights should be programmed by pulse counts computed from the device model, not by writing arbitrary conductance values.
  • Gradient-derived three-factor rules, with their third factor carrying error, surprise, or reward, should replace classical STDP for online learning on RRAMs, since STDP lacks a modulation term and is an incomplete description of plasticity.
  • The asymmetric nonlinearity of RRAM potentiation and depression can be compensated by inverting the exponential conductance model; the cost is a read operation per update and a trade-off between training time and update-circuit complexity.
  • Independent read and write variability and blank-out synapses can help learning by providing stochasticity, while fixed pattern noise must be modeled or corrected because it acts as per-weight learning-rate variation.
  • Practical systems will likely use semi-online training: transfer weights trained offline, then retrain briefly on-chip to recover accuracy after device impairments, reducing endurance requirements.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The pulse-count compensation method is not limited to ICA: any three-factor rule whose desired update can be expressed as a target $\Delta w$ could in principle be compiled into per-device pulse counts, turning the exponential model into a sort of programming compiler for RRAM-based learning.
  • Because the scheme requires reading the present conductance before every update, it implies a read-before-write protocol; a testable extension would be to compare exact pulse counting against approximate update rules that skip the read and measure the resulting accuracy and energy cost.
  • If device stochasticity is treated as a feature rather than noise, the same crossbar could implement approximate Bayesian inference via synaptic sampling; the paper gestures in this direction but does not formalize a memristor-specific sampling rule.
  • Applying the same pulse-count logic to supervised rules such as eRBP or DECOLLE would provide a direct hardware test of whether gradient-derived three-factor rules retain their accuracy when the device, not a digital model, performs the update.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper is a chapter-style review of spiking neural networks (SNNs) and their implementation with memristive crossbars. It develops discrete-time leaky integrate-and-fire (LI&F) dynamics, describes crossbar-based vector-matrix multiplication, and surveys memory/device non-idealities including weight mapping, endurance, retention, sneak paths, delay, and asymmetric nonlinear conductance updates. The central design proposal is that three-factor learning rules should be matched to the device's update dynamics, and that pulse-count compensation derived from an exponential RRAM model can make the device 'behave as required' for gradient-based learning. The proposal is illustrated with an online independent component analysis (ICA) example, and the chapter then reviews gradient-based three-factor rules (eRBP, SuperSpike, DECOLLE, EGHR) and stochastic SNN approaches.

Significance. If the central design prescription is valid, the chapter offers a useful perspective: memristors should not be treated as drop-in memory, and learning rules should be co-designed with device update dynamics so that pulse-count compensation can map three-factor gradient rules onto strongly nonlinear RRAM devices. The algebraic inversion of the exponential update model in Sec. 3.5.2 is transparent, the linearized form is explicitly stated, and the survey of non-idealities and of gradient-based SNN learning is a valuable pedagogical contribution. The main weakness is that the 'exact realization' claim is validated only against the same model used to derive the compensation, and the chapter's own documented non-idealities are not propagated into the ICA demonstration, so the empirical support for the central claim is currently limited.

major comments (3)
  1. [Sec. 3.5.2, Eqs. (13)-(17), Fig. 10] The central design claim—that programming with the pulse counts of Eqs. (23)-(24) makes the RRAM 'behave as required' and exactly realizes the three-factor update—is not supported by the evidence presented. The derivation of Eqs. (14)-(15) inverts the update model of Eq. (13), which is itself a consequence of the fitted exponential model Eq. (8). The simulation in Fig. 10 generates conductance with that same model and then compensates using the same model, so it verifies the algebraic inversion rather than the robustness of the physical realization. Moreover, Eqs. (14)-(15) require accurate knowledge of the current conductance G(n) and of alpha_P, alpha_D, Gmax, and Gmin; the chapter itself documents violations of this assumption: Sec. 3.3 shows that sneak paths distort the read currents in a location-dependent way (Fig. 4), and Sec. 3.5.1 assigns a 25% tolerance to alpha and independent variation to Gmax and Gmin. No experiment or simulation in the manuscript injects read noise or parameter mismatch between the controller and the device, so the claim that the learning rule can be 'realized exactly' on the device is unverified. A sensitivity analysis, or a version of Fig. 10 with perturbed parameters/readouts, is needed before this prescription is presented as established.
  2. [Sec. 2, discrete-time LI&F equations] The discrete-time LI&F model is internally inconsistent. The text states that alpha = exp(-Delta_t/tau_mem) and beta = exp(-Delta_t/tau_syn), but the update equations read Ui[n+1] = beta Ui[n] + ... and Ii[n+1] = alpha Ii[n] + ..., so the symbols alpha and beta are swapped relative to their definitions. This is not merely typographical: Sec. 5.2 subsequently refers to alpha and beta when discussing the need for filtering and the alpha = beta = 0 case, so the mismatch propagates to the hardware discussion. The definitions or the equations must be aligned.
  3. [Abstract and Sec. 4, three-factor versus STDP comparison] The abstract's claim that multifactor plasticity rules 'generally show much higher performance' than classical STDP is stronger than the evidence reviewed in the chapter. The paper presents specific results for eRBP, DECOLLE, and ICA, but it does not provide a systematic comparison with STDP on common benchmarks, and the statement in the abstract is presented without qualification. Please either moderate the claim to reflect the reviewed evidence or add comparative results that substantiate it.
minor comments (5)
  1. [Sec. 2, before Eq. (1)] The sentence 'tau_mem and tau_syn are the membrane time constants' should read 'are the membrane and synaptic time constants.'
  2. [Sec. 3.5, Eq. (8)] The depression branch of Eq. (8) uses alpha_1 in the exponent; given the following text and the definitions alpha_P = |Vp| alpha_1 T and alpha_D = |VD| alpha_2 T, this should be alpha_2.
  3. [Sec. 3.5, Eq. (11)] The signs in the exponents of Eq. (11) are wrong: differentiating Eqs. (9)-(10) gives beta_P alpha_P e^{-alpha_P n} and -beta_D alpha_D e^{-alpha_D n}. Please correct.
  4. [Sec. 3.3, around Fig. 4] The phrase 'the measured weights should be similar to the measured weights' should read 'similar to the desired weights.'
  5. [Sec. 5.2, modulation paragraph] The sentence beginning 'the weight update can consist in the two factors (epsilon_pre * S_j)), where M_i rho'(U_i)' is incomplete; it should express that the update is the product of (epsilon_pre * S_j) and M_i rho'(U_i).

Circularity Check

1 steps flagged · score 6.0 of 10

Pulse-count compensation is validated by the same fitted exponential model it inverts; the 'circuit behaves as required' claim reduces to construction.

  1. self definitional [Sec. 3.5.2, Eqs. (13)-(17), (23)-(24), Fig. 10]
    "In [Fouda et al., 2019], we proposed a method to have the resistive devices behave exactly like the learning rule where the change in each weight must be proportional to the change in the RRAM’s conductance, ∆G∝ ∆w. ... By programming the RRAMs using the previous equations, the circuit behaves as required and compensates for the asymmetric nonlinearity of the devices."

    Equations (23)-(24) are obtained by substituting the target update Δw into the inverse of Eq. (13), which is itself just the exponential model Eq. (8) fitted to one Mo/TiOx/TiN device (Tables 1-2). The only validation offered, Fig. 10, is a simulation 'Reproduced from [Fouda et al., 2019]' in which the same exponential model generates the conductance changes and the same inverse computes the pulse counts. The observed 'circuit behaves as required' is therefore a bookkeeping identity: any desired ΔG is realized by construction if the model and parameters are correct. It does not test the model against real devices, parameter estimation errors, or read noise; the paper itself reports 25% α variation and sneak paths that would break the inverse.

full rationale

The survey portions of the chapter are largely self-contained: the three-factor rule formalism in Sec. 4.1 is derived from gradient descent over spiking neuron models with citations to external and independent work (Pfister et al. 2006, Urbanczik and Senn 2014, Zenke and Ganguli 2017), and the learning-rule discussions (eRBP, SuperSpike, DECOLLE, EGHR) are presented with their own equations and benchmarks rather than being reduced to the chapter's inputs. No circularity appears there. The circularity is localized to Sec. 3.5.2: the pulse-count compensation is constructed by inverting the fitted exponential RRAM update model, and the only demonstration that the circuit 'behaves as required' (Fig. 10) is a simulation reproduced from the authors' own Fouda et al. 2019 that uses that same model to generate the conductance changes. Thus the compensation result is equivalent to the assumed model by construction; it cannot validate the model or the exact-realization claim independently. The paper itself identifies assumptions that would break the identity, including 25% α tolerance, device-to-device variability, and crossbar sneak paths, but does not quantify their effect on the claimed exact realization. This is a partial circularity in the validation of the central RRAM-specific design claim, not in the general learning-theoretic content. Therefore the score is 6 rather than higher: the learning-rule derivations retain independent content, while one load-bearing 'prediction' reduces to the fitted model by construction.

Assumptions & free parameters 8 free parameters · 7 assumptions · 0 invented entities

The chapter adds no new physical or mathematical entities; it recombines established models (LIF, crossbar VMM, three-factor rules) with an empirically fitted exponential RRAM update model. The load-bearing free parameters are the fitted device coefficients and their Vp-interpolations, hand-chosen variation tolerances, and simulation settings; the load-bearing axioms are the adequacy of the LIF model, the adequacy of the exponential update model, and the transferability of surrogate-gradient and EGHR convergence results to memristor hardware.

free parameters (8)
  • alpha_P (potentiation rate coefficient) = 30.58e-3, 18.23e-3, 19.19e-3 for Vp = 3V, 2.5V, 2V
    Fitted to measured Mo/TiOx/TiN conductance curves in Table 1; used in Eqs. (9)-(17) for pulse-count updates.
  • alpha_D (depression rate coefficient) = 353.4e-3, 35.29e-3, 20.55e-3 for Vp = -3V, -2.5V, -2V
    Fitted to measured depression curves in Table 2; used in Eqs. (10)-(17).
  • beta_P and beta_D (LTP/LTD scaling coefficients) = beta_P: 626.8e-9, 220.22e-9, 71.7e-9; beta_D: 921.9e-9, 410.9e-9, 330.8e-9 (same voltage sets)
    Fitted scaling parameters in the exponential update model (Eq. 8), Tables 1-2.
  • Gmax and Gmin (conductance bounds) = Gmax: 674, 252.7, 83.38 nS; Gmin: 32.95, 186.3, 340.5 nS
    Fitted per programming voltage in Tables 1-2; define the operating range for the weight mapping (Eq. 5).
  • Vp-interpolation functions for model coefficients = e.g., alpha_P = 2.968 e^{1.823 Vp} - 30.4; alpha_D = 8.14e-6 e^{-5.48 Vp} + 20.5
    Fitted to the three characterized voltages; used to extrapolate device behavior to non-reported programming voltages.
  • Variability tolerances for device variation simulation = 25% for alpha, 1% for Gmax, 5% for Gmin, lognormal beta
    Chosen by hand in Sec. 3.5.1 for the variation simulation in Fig. 7b; not derived from measured statistics.
  • ICA test bench settings = mixture angle theta = pi/6, two Laplacian sources, 10^4 samples, scaling learning rate eta' (value not stated)
    Settings for the online ICA demonstration in Fig. 10; success is reported qualitatively.
  • Crossbar simulation parameters for sneak path = wire resistance 0.1 ohm in Fig. 4; 92 ohm at 5nm node, 10 ohm/cell estimates in Sec. 3.3
    Inputs to the sneak path simulation; the 0.1 ohm value is small but the effect is shown to be large, motivating partitioning.
assumptions (7)
  • domain assumption Leaky Integrate-and-Fire dynamics (Eqs. 1-2) adequately model neuromorphic neurons.
    Used throughout as the base model for hardware neurons; standard in the cited literature.
  • standard math Discrete-time LIF with step-function reset is equivalent to the continuous form.
    Sec. 2 derives the discrete update equations used for the RNN and perceptron views of SNNs.
  • domain assumption RRAM conductance update follows an exponential model (Eq. 8) with constant coefficients per device and voltage.
    Assumed to describe potentiation and depression for RRAM families; fitted to one device at three voltages and interpolated in Vp.
  • domain assumption Signed weights can be represented by conductance differences G = G+ - G- with bounds Gmin <= G <= Gmax and equal-pair mapping.
    Standard design choice from the memristive crossbar literature; used in Eq. (5) and the mapping optimization in Eq. (6).
  • domain assumption Three-factor rules derived via surrogate gradients approximate gradient descent over LIF dynamics.
    Inherited from cited work (Zenke and Ganguli 2017, Neftci et al. 2019); the chapter relies on this to claim near-backprop performance for eRBP and DECOLLE.
  • standard math EGHR converges to the ICA solution (weights proportional to A^{-1}).
    Proved mathematically in Isomura and Toyoizumi 2016; the chapter relies on it for Eqs. (23)-(24).
  • domain assumption Blank-out synapse stochasticity improves learning performance and is naturally available in memristive devices.
    Sec. 5 claims stochasticity can be exploited as regularization, citing prior simulation work and not hardware demonstrations in this chapter.

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Cite this review

Pith. "Pith review of Spiking Neural Networks for Inference and Learning: A Memristor-based Design Perspective." pith.science (2026). https://pith.science/paper/LATT5EJV

@misc{pith2026190901771,
  author       = {Pith},
  title        = {Pith review of: Spiking Neural Networks for Inference and Learning: A Memristor-based Design Perspective},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/LATT5EJV}},
  note         = {Machine review of arXiv:1909.01771}
}
read the original abstract

On metrics of density and power efficiency, neuromorphic technologies have the potential to surpass mainstream computing technologies in tasks where real-time functionality, adaptability, and autonomy are essential. While algorithmic advances in neuromorphic computing are proceeding successfully, the potential of memristors to improve neuromorphic computing have not yet born fruit, primarily because they are often used as a drop-in replacement to conventional memory. However, interdisciplinary approaches anchored in machine learning theory suggest that multifactor plasticity rules matching neural and synaptic dynamics to the device capabilities can take better advantage of memristor dynamics and its stochasticity. Furthermore, such plasticity rules generally show much higher performance than that of classical Spike Time Dependent Plasticity (STDP) rules. This chapter reviews the recent development in learning with spiking neural network models and their possible implementation with memristor-based hardware.

Figures

Figures reproduced from arXiv: 1909.01771 by the authors.

Figure 1
Figure 1. a)Example Leaky Integrate & Fire Neuron dynamics for [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Crossbar array realization of one layer neural network. [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Mapping synaptic weight into conductances. [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (8 more)
Figure 4
Figure 4. Figure 4: Effect of the wire resistance on the measured weights for [PITH_FULL_IMAGE:figures/full_fig_p007_4.png]
Figure 5
Figure 5. Figure 5: Realization of the partitioned matrices. [PITH_FULL_IMAGE:figures/full_fig_p008_5.png]
Figure 6
Figure 6. Figure 6: RRAM’s conductance update (a) long term potentiation (b) long term depression. Reproduced [PITH_FULL_IMAGE:figures/full_fig_p011_6.png]
Figure 7
Figure 7. Figure 7: Non-idealities of the RRAM:(a) asymmetric nonlinear weight update (b) device Variations. Re [PITH_FULL_IMAGE:figures/full_fig_p011_7.png]
Figure 8
Figure 8. Figure 8: Network Architecture for Event-driven Random Backpropagation (eRBP). The network consists of feed-forward layers (784-200-200-10) for prediction and feedback layers for supervised training with labels (targets) L. Full arrows indicate synaptic connections, thick full a…
Figure 9
Figure 9. Figure 9: Deep continuous local learning example. (Left) Each layer consists of spiking neurons with contin￾uous dynamics. Each layer feeds into a local classifier through fixed, random connections (diamond-shaped, y). The classifier is trained to produce auxiliary targets yˆ. E…
Figure 10
Figure 10. Figure 10: The online training results versus training time (a) Evolution of the weights, and (b) Visual [PITH_FULL_IMAGE:figures/full_fig_p018_10.png]
Figure 11
Figure 11. Figure 11: The Synaptic Sampling Machines (SSM). (a) At every occurrence of a pre-synaptic event, a [PITH_FULL_IMAGE:figures/full_fig_p019_11.png]

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Pith tools

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