Experimental realization of the bucket-brigade quantum random access memory

Anbang Wang; Aosai Zhang; Chao Song; Chuanyu Zhang; Debin Xiang; Fanhao Shen; Gongyu Liu; Hekang Li; Jianan Yang; Jianwei Yin

REVIEW 2 major objections 4 minor 57 references

Experimental realization of the bucket-brigade quantum random access memory

T0 review · 2 major / 4 minor · reviewed 2026-08-15 · deepseek-v4-flash

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Pith's one-line read Quantum RAM queries hit 80 percent fidelity on a superconducting chip.

desk verdict First full multi-layer bucket-brigade QRAM on a superconducting processor, with reusable router decompositions—worth a serious referee, but the post-selection and the SI proof both need tightening. read the letter →

arxiv 2506.16682 v1 pith:LTU25I2T submitted 2025-06-20 quant-ph

Fanhao Shen , Yujie Ji , Debin Xiang , Yanzhe Wang , Ke Wang , Chuanyu Zhang , Aosai Zhang , Yiren Zou

show 15 more authors

Yu Gao Zhengyi Cui Gongyu Liu Jianan Yang Yihang Han Jinfeng Deng Anbang Wang Zhihong Zhang Hekang Li Qiujiang Guo Pengfei Zhang Chao Song Liqiang Lu Zhen Wang Jianwei Yin

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classification quant-ph

keywords bucket-brigadequantumrandomaccessmemorysuperconductingprocessorerrormitigationteleportationgatedecompositionnoiseresiliencequeryfidelity

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper reports the first end-to-end experimental realization of a bucket-brigade quantum random access memory (QRAM) on a programmable superconducting processor, for two- and three-layer memory trees holding four and eight classical bits. The authors argue that a QRAM, which lets a quantum computer read classical data in superposition, is a prerequisite for quantum speedup in many algorithms, and that until now almost all evidence for the bucket-brigade design was theoretical. Their experiments achieve post-selected query fidelities up to 0.800 ± 0.026 for two layers and 0.604 ± 0.005 for three layers, and they present the first experimental evidence that errors in the unqueried branches stay localized rather than spreading into the queried data. If the architecture scales as the simulations suggest, near-term superconducting processors could serve as practical QRAM devices for quantum algorithms.

What carries the argument

The load-bearing object is the bucket-brigade tree of quantum routers, each acting as a four-body routing operation that sends the data bus left or right depending on the address qubit. The paper's technical engine is a hardware-efficient gate decomposition: because routing occurs only in restricted subspaces, the full controlled-SWAP can be replaced by a functionally equivalent unitary that requires fewer CZ gates depending on connectivity, reducing total CZ depth by over 30%. Quantum teleportation of the data bus between layers preserves the O(log N) latency on a 2D grid. The error-mitigation machinery uses the router qubits themselves as error indicators: after a complete query they should be disentangled and in |0>, so post-selecting on that outcome filters out error events without additional circuits.

What would settle it

Perform a full two-layer query on a known address-data state, then measure every router qubit in the X basis as well as the Z basis and reconstruct the address-data state conditioned on each router outcome; if the conditioned state depends on which router basis was measured, or if post-selecting on |0> routers changes the address-data density matrix more than the known readout-error budget allows, the disentanglement assumption is violated and the reported post-selected fidelities are biased.

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Extended reading notes

Core claim

The central claim is that a bucket-brigade QRAM, a binary tree of quantum routers that directs a quantum signal to the memory cell named by a quantum address, can be built and run on a square-grid superconducting processor while preserving the architecture's logarithmic time scaling and noise resilience. To do this, the authors replace the conventional controlled-SWAP-based router with a functionally equivalent unitary that needs only 10 CZ gates in the most favorable connectivity, cutting circuit depth by more than 30%, and they use quantum teleportation to connect layers without an exponentially growing communication cost. They then exploit the fact that router qubits return to |0> after a full query cycle: measuring them and discarding runs in which any router is excited raises the two-layer fidelity from an average near 0.64 to 0.800 ± 0.026, and improves a GHZ-state preparation fidelity by over 0.13. In a three-layer system, injecting depolarizing errors into a queried router degrades fidelity roughly linearly with slope -0.2549, while the same errors in distant unqueried branches are nearly harmless with slope -0.0053, which the authors take as direct experimental evidence for the localization of errors and the origin of the architecture's noise resilience.

Load-bearing premise

The whole error-mitigation and fidelity-reporting scheme assumes that after a complete query the router qubits are perfectly disentangled from the address and data registers and sit in |0>, so measuring them and keeping only the |0> outcomes removes errors without touching the queried state; any residual entanglement would bias the reported fidelities upward.

Editorial extensions

If this is right

The more-than-30% reduction in CZ depth directly lowers the noise burden of each query, making deeper QRAM trees more feasible on current hardware.
The router-qubit error mitigation boosts query fidelity across all address superpositions and doubles as a diagnostic that can identify which branches of the memory suffered errors.
The measured branch-dependence of error sensitivity confirms that errors in unqueried branches are largely shielded, supporting the theoretical polylogarithmic infidelity scaling of the bucket-brigade design.
Numerical scalability analysis predicts that the gate error rate needed for a fixed target fidelity decays as a power law with exponent about -2.688 in the number of layers, suggesting that error-corrected superconducting processors could run large QRAMs.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The reported 0.800 fidelity is the post-selected number; the raw average for two-layer queries is about 0.64, so the true hardware performance before error mitigation remains a significant gap that future demonstrations will need to close.
The teleportation step used in the two-layer demo is post-selected on a Bell-state outcome rather than feed-forward corrected; the paper notes feed-forward would be needed for scalability, so a natural next experiment is to close that loophole.
Because the gate decomposition exploits QRAM-specific subspace constraints, the same optimization could be imported into other memory architectures built from routing trees wherever controlled-SWAP gates appear.
The error-localization evidence suggests a practical systems-level rule: place the most error-prone physical qubits in the deepest, least-queried branches of the tree, where their noise is most shielded from the queried path.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

The headline: this is the first full multi-layer bucket-brigade QRAM query on a programmable superconducting processor, and it deserves serious referee time. The two- and three-layer demonstrations—post-selected query fidelities of 0.800±0.026 and 0.604±0.005—are internally consistent, with error bars and readout calibration. The router decomposition work is genuinely reusable.

What's actually new: the subspace-adapted router unitaries (U', U'', U''') cut CZ depth by more than 30% versus controlled-SWAP (10 CZ vs 16 in the key configuration), with QASM files posted. They verify the optimized unitaries against the controlled-SWAP implementation, so the benchmark isn't circular. The teleportation-based mapping cleanly answers the H-tree latency problem on a 2D grid; their teleportation fidelity, 0.994±0.005, is solid. The three-layer error-injection data in Fig. 3a—queried path degrades roughly 12x faster than unqueried paths—are the clearest experimental evidence to date for bucket-brigade error localization, and the entanglement-entropy measurement in Fig. 3b complements it. The router post-selection error mitigation is simple and effective, and the citation pattern is fair; the router-only precursors and theory papers are all credited.

Minor: the scalability exponent α≈−2.688 is model-dependent (hand-set es/et=1/10, Pauli depolarizing), and the data and code are not public yet. For an experimental milestone, data availability should be a publication condition.

Moderate: the post-selection bias concern is real, though it doesn't kill the paper. Routers fully disentangled from address/data after a full cycle is an ideal-circuit statement; under gate noise the router-|0> syndrome is an imperfect proxy for 'no error occurred,' so the post-selected fidelities may be inflated. The missing check is a noisy simulation comparing projective post-selection with exact conditioning on simulated error flags. It should be added; the qualitative findings will likely survive.

Moderate: the SI error-mitigation proof has a genuine gap. Eq. S20 treats DK (no errors in the first K router layers) as if it were contained in Kr (first K routers end in |0>). It isn't—deeper errors can propagate up and excite a shallower router. The later replacement p(Kr) ≈ Σ_{c in DK} p(c) + O(ε) is asserted, not derived. The result is probably salvageable for small ε, and Fig. S2 backs the qualitative claim, but the proof needs tightening.

Who it's for: experimental quantum-architecture groups, QRAM theorists, and algorithm people who need honest near-term QRAM numbers. My recommendation: engage with it, send it to peer review, and require the SI fix, the bias check, and public data. The core demonstration is a genuine step forward.

Referee Report

2 major / 4 minor

Summary. The paper reports an experimental implementation of a bucket-brigade QRAM on a superconducting processor. The authors introduce a hardware-efficient gate decomposition for the quantum routing operation that reduces the CZ depth relative to controlled-SWAP-based routing, use quantum teleportation to preserve logarithmic query depth when mapping the binary-tree architecture onto a square grid, and demonstrate two- and three-layer QRAM queries with fidelities up to 0.800 ± 0.026 and 0.604 ± 0.005. They also propose an error-mitigation protocol that post-selects on all router qubits being in |0>, study error propagation by injecting depolarizing errors on individual routers, and use noisy simulations to extrapolate the query fidelity to larger QRAM sizes.

Significance. If the central claims hold, this is a valuable experimental step: it is one of the first end-to-end demonstrations of a bucket-brigade QRAM on a programmable superconducting processor. The hardware-efficient routing decomposition, the teleportation-based layout, and the error-localization measurements in Fig. 3a are concrete contributions with explicit resource counts in SI Table I. The paper is also honest about what is simulated versus measured, and the data availability statement is a plus. However, the error-mitigation protocol is load-bearing for the headline fidelity numbers, and its validity depends on an ideal disentanglement assumption that is only approximately satisfied under noise; the current manuscript does not supply the missing check.

major comments (2)

[Main text, 'QRAM performance' (Fig. 2c–2e)] The error-mitigated fidelities are obtained by measuring all router qubits after the full query and keeping only shots where every router is in |0>. The unbiasedness of this post-selection relies on the claim that the router qubits are completely disentangled from the address and data registers before and after a full query cycle. Under gate noise this disentanglement is only approximate: errors can leave residual correlations between a router's |0>/|1> degree of freedom and the address/data state, so projective router measurement can condition the retained state on a syndrome that does not coincide with 'no error occurred'. The paper provides no independent check of this, such as a noisy simulation comparing projective post-selection with exact conditioning on simulated error flags, or a comparison of post-selected and unconditioned fidelities against a simulated ground truth. Because the headline numbers (0.800 ± 0.026 for two-layer queries and the improvements in Figs. 2c–2e) all use this post-selection, this gap is load-bearing for the main experimental claim.
[SI Sec. I.B, Eqs. (S20)–(S22)] The proof that partial-layer post-selection is scalable and improves fidelity is not rigorous. The event DK = {no errors in the first K router layers} is not contained in Kr = {the first K router layers end in |0>}, because errors in deeper layers can propagate upward and flip routers in the first K layers; conversely, some errors in the first K layers, such as phase errors on routers in superposition states, may not be detected by a Z-basis |0> measurement. The later replacement of p(Kr) by sum_{c in DK} p(c) + O(epsilon) is therefore not justified. Since this is the basis for the claim that the method 'possesses a certain degree of scalability' and for Eq. (S22), the scalability conclusion is not established by the present argument.

minor comments (4)

[Main text, Conclusion] The conclusion states that the bucket-brigade QRAM 'exhibits polylogarithmic scaling of query infidelity with respect to gate errors', but the SI bound (Eq. S16) is polylogarithmic in the memory size N and linear in the gate error rate; this wording should be corrected to avoid conflating the two scalings.
[SI Sec. I.B] The sample-size estimate around Eq. (S17) should clarify that the post-selection probability p(Kr) is itself estimated from the same data, so the confidence statement is approximate; this is a statistical presentation issue rather than a technical flaw.
[Figure 1c] The caption of Fig. 1c should specify whether the CZ-depth comparison for the H-tree recursive mapping includes the teleportation overhead; as written, the comparison between the two approaches is ambiguous.
[Throughout] The manuscript contains several OCR/garbled-character artifacts, for example in the author list and in the Supplementary Information equations and figures; these need to be cleaned before publication.

Circularity Check

0 steps flagged · score 0.0 of 10

No circular derivation found: central fidelities are externally benchmarked against ideal states; the only self-citation is a non-load-bearing device-layout reference, and the SI proof gap is a correctness concern, not circularity.

full rationale

The paper's central derivations are not circular. The query fidelities in Fig. 2c are measured against the ideal address-data state |psi_ideal> defined by the QRAM transformation, so the headline numbers are externally benchmarked rather than fitted to the model being claimed. The optimized router unitaries U', U'', U''' are obtained by explicitly constraining the routing subspace, synthesizing with the external tool Cpflow, and comparing CZ counts with controlled-SWAP decompositions; the >30% depth reduction is a direct circuit-count comparison, not an output of the fidelity claims. The three-layer error-injection experiment measures fidelity slopes with and without injected depolarizing errors, and the entanglement-entropy data come from direct quantum state tomography; neither presupposes the localized-error-propagation conclusion. The O(log^3 N) infidelity bound in SI Section I A is an extension of the prior Hann et al. framework and is checked by an independent noisy simulation. There is one minor self-citation: SI Section II A references the same group's earlier processor paper ([11]) for the device layout, but this only describes hardware and is not load-bearing for the QRAM results. Two correctness concerns are real but are not circularity: the router post-selection assumes near-disentanglement of routers after a full query cycle, and the SI error-mitigation derivation (Eqs. S20-S22) does not rigorously justify replacing p(Kr) with sum_{c in DK} p(c) + O(epsilon), because deeper errors may propagate upward into the measured router layers. These are unsupported-inference or proof-gap issues, not reductions of a prediction to its input by construction. Therefore no significant circularity is present.

Assumptions & free parameters 2 free parameters · 5 assumptions · 0 invented entities

No new physical entities are introduced. The optimized routing unitaries are mathematical circuit-level objects, and the free parameters are simulation modeling choices (es/et ratio) plus a fitted scaling exponent. The load-bearing assumptions are experimental (router disentanglement), computational (noise model, sparse gate set), and architectural (feedforward teleportation).

free parameters (2)

es/et ratio = 0.1
In noisy simulations, the single-qubit Pauli error rate es is fixed at one tenth of the two-qubit error rate et (Methods, Numerical simulation). This hand-set ratio is an input to the scaling predictions in Fig. 3c and Extended Data Fig. 2.
Scaling exponent alpha = -2.688
Fit to the simulated gate-error thresholds in Extended Data Fig. 2. It is a reported result of the scalability analysis, not an input parameter, but it is a number fitted to simulation data and depends on the depolarizing noise model.

assumptions (5)

domain assumption An ideal full QRAM query cycle leaves all router qubits disentangled from the address and data registers, in the state |0>.
Main text, 'QRAM performance' states router qubits are disentangled and in the ground state after a full query, justifying measurement of routers as error indicators without disturbing the address/data state; the error-mitigation results (Figs. 2c-2e) depend on this.
domain assumption Depolarizing Pauli error channels with es = et/10 capture the relevant noise for scalability simulations.
Methods, Numerical simulation; the scaling contour in Fig. 3c and the alpha = -2.688 estimate are computed under this model.
domain assumption The gate set {SWAP, U_CSWAP, H, X} maps each computational basis component within {|0>, |1>, |+>, |->}, preserving efficiently computable sparse simulation.
Methods, Numerical simulation; this property is what makes the O(N_A log N) simulation possible.
domain assumption In the infidelity proof, every gate error rate can be elevated to the CSWAP error rate, and idle gates have error comparable to single-qubit gates.
Supplementary Information I.A sets all gate errors equal to the CSWAP rate to derive the O(log^3 N) infidelity bound; conservative but not derived from a device.
domain assumption Teleportation post-selection on the |Phi+> outcome can be replaced by classical feedforward in a scalable device.
Methods, Quantum teleportation states post-selection can be replaced by feedforward; the scalable mapping claim assumes this replacement.

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Pith. "Pith review of Experimental realization of the bucket-brigade quantum random access memory." pith.science (2026). https://pith.science/paper/LTU25I2T

@misc{pith2026250616682,
  author       = {Pith},
  title        = {Pith review of: Experimental realization of the bucket-brigade quantum random access memory},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/LTU25I2T}},
  note         = {Machine review of arXiv:2506.16682}
}

abstract

Quantum random access memory (QRAM) enables efficient classical data access for quantum computers -- a prerequisite for many quantum algorithms to achieve quantum speedup. Despite various proposals, the experimental realization of QRAM remains largely unexplored. Here, we experimentally investigate the circuit-based bucket-brigade QRAM with a superconducting quantum processor. To facilitate the experimental implementation, we introduce a hardware-efficient gate decomposition scheme for quantum routers, which effectively reduces the depth of the QRAM circuit by more than 30% compared to the conventional controlled-SWAP-based implementation. We further propose an error mitigation method to boost the QRAM query fidelity. With these techniques, we are able to experimentally implement the QRAM architectures with two and three layers, achieving query fidelities up to 0.800 $\pm$ 0.026 and 0.604$\pm$0.005, respectively. Additionally, we study the error propagation mechanism and the scalability of our QRAM implementation, providing experimental evidence for the noise resilience nature of the bucket-brigade QRAM architecture. Our results highlight the potential of superconducting quantum processors for realizing a scalable QRAM architecture.

Figures

Figures reproduced from arXiv: 2506.16682 by the authors.

**Figure 1.** Experimental implementation of QRAM with a superconducting quantum processor. a, Schematic of the two-layer bucketbrigade QRAM, which can query four classical data bits, denoted as x00, x01, x10, and x11, according to the query address. The qubits in the QRAM routers can be divided into two groups, one for storing the address information, and the other for loading the data bus. The data bus encode the data bit in t… view at source ↗

**Figure 2.** Experimental quantum teleportation and QRAM performances. a, The six quantum states used in the teleportation experiment and the quantum circuit of teleportation. The state in the source qubit (Qs ) is transferred to the data qubit (Qd ) through the ancillary qubit (Qa ). b, The teleportation fidelities of the six quantum states, calculated as F ≡ Trq ρ 1/2 out σinρ 1/2 out 2 , where ρout is the experimentally ob… view at source ↗

**Figure 3.** Error analysis on the three-layer bucket-brigade QRAM architecture. a, Experimental query fidelity under depolarizing errors with varying Pauli error rates. Each time, we inject the depolarizing errors into one of the router qubits located at the third level, labeled from 1 to 4, after the data loading operation. Inset shows the schematic of the three-layer QRAM, with the queried branch highlighted. Error bars denot… view at source ↗

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The router qubits in QRAM are disentangled from the ad- dress and data registers and remain in the ground state be- fore and after a full cycle of query operation

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Pith tools

Reviewed August 15, 2026 · model on record in the stance chip above.

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The router qubits in QRAM are disentangled from the ad- dress and data registers and remain in the ground state be- fore and after a full cycle of query operation

019 for two- and four-component addresses. The router qubits in QRAM are disentangled from the ad- dress and data registers and remain in the ground state be- fore and after a full cycle of query operation. As a result, we can measure the router qubits after query without disturb- ing the quantum state in the address and data registers, and any population...

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In contrast, error injection in the three unqueried paths demonstrates signiﬁcantly more gradual ﬁdelity decline (average slope k = −0

0108). In contrast, error injection in the three unqueried paths demonstrates signiﬁcantly more gradual ﬁdelity decline (average slope k = −0. 0211 ± 0. 0069), with the rate of degradation exhibiting a clear spatial dependence. Remark- ably, the rightmost branch, which is maximally distant from the queried path, shows nearly error-immune behavior (slope k...

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688) as the number of QRAM layers in- creases, despite the exponential growth in system qubits (see Supplementary Information for further analysis)

Remarkably, the required gate error rate to maintain a target query ﬁdelity follows a power- law decay (α ≈ − 2. 688) as the number of QRAM layers in- creases, despite the exponential growth in system qubits (see Supplementary Information for further analysis). The results suggest that, with the future inclusion of quantum error cor- rection techniques th...

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