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arxiv 1811.01693 v2 pith:LZAA7JLX submitted 2018-11-05 quant-ph

The electronic interface for quantum processors

classification quant-ph
keywords quantuminterfaceelectroniccomputerscryogenicprocessorschallengesimplementations
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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Quantum computers can potentially provide an unprecedented speed-up with respect to traditional computers. However, a significant increase in the number of quantum bits (qubits) and their performance is required to demonstrate such quantum supremacy. While scaling up the underlying quantum processor is extremely challenging, building the electronics required to interface such large-scale processor is just as relevant and arduous. This paper discusses the challenges in designing a scalable electronic interface for quantum processors. To that end, we discuss the requirements dictated by different qubit technologies and present existing implementations of the electronic interface. The limitations in scaling up such state-of-the-art implementations are analyzed, and possible solutions to overcome those hurdles are reviewed. The benefits offered by operating the electronic interface at cryogenic temperatures in close proximity to the low-temperature qubits are discussed. Although several significant challenges must still be faced by researchers in the field of cryogenic control for quantum processors, a cryogenic electronic interface appears the viable solution to enable large-scale quantum computers able to address world-changing computational problems.

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