Paper Citation Record · LEDGER

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation

As of 17 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 6 inbound Pith citation observations for arXiv:2503.15112.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2503.15112 v1

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 6 of 6 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-17T06:30:58.91139+00:00

measured 6 of 6 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-16T11:22:02.335336Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-07-03T19:08:49.826547Z

Reference resolution

0 of 0 outbound references displayed

verified exact0
verified fuzzy0
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation c266b73f-8f04-4648-82b9-a2e743b2b97d · inbound

Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback cites this paper.

Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation

Reference 20

Resolution: unresolved; no resolver link, observed 2026-08-16T11:22:02.335336Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ea25378d-a37b-4a9a-98e1-80ba1852acef · inbound

Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification cites this paper.

Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-15T19:59:24.431514Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 52d62811-6a4e-443e-b6ca-4d0006244cbc · inbound

Alpha-RTL: Test-Time Training for RTL Hardware Optimization cites this paper.

Alpha-RTL: Test-Time Training for RTL Hardware Optimization OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation

Reference 15

Resolution: verified exact; arxiv_id, observed 2026-07-02T07:06:44.160975Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 88f9faa0-bcff-4d2a-ba32-42be855da637 · inbound

PDAGENT-BENCH: Characterizing, Grounding, and Architecting LLM Agents for VLSI Physical Design cites this paper.

PDAGENT-BENCH: Characterizing, Grounding, and Architecting LLM Agents for VLSI Physical Design OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation

Reference 18

Resolution: verified exact; arxiv_id, observed 2026-07-03T19:08:49.828010Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 0baa6c8f-965e-4c4f-8aab-d73d0d500d31 · inbound

Agentic Hardware Design as Repository-Level Code Evolution cites this paper.

Agentic Hardware Design as Repository-Level Code Evolution OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation

Reference 9

Resolution: metadata mismatch; arxiv_id, observed 2026-07-01T18:45:58.321181Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation ddbc3ea5-1f4d-4be8-bff1-0d8271cd981d · inbound

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing cites this paper.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-16T00:08:22.489390Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.