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REVIEW 3 major objections 5 minor 84 references

Learning-based PCB routing can approach mature rule-based routers when agents act through the EDA engine's native operations in a closed loop, fed by design-rule-check feedback, rather than on grid abstractions or one-shot generation.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

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T0 review · deepseek-v4-flash

2026-08-04 04:27 UTC pith:OUMEFHAK

load-bearing objection The environment is a genuine contribution, but the zero-shot transfer headline rests on DRC rules partly inferred from the reference routings themselves, so treat the D3 numbers as upper bounds until that is resolved. the 3 major comments →

arxiv 2607.05915 v2 pith:OUMEFHAK submitted 2026-07-07 cs.AI

PCBWorld: A Benchmark Environment for Engine-Grounded PCB Design Automation

Hyungseok Song , Junseok Park , Won-Seok Choi , Seohui Bae , Han-Seul Jeong , Youngjoon Park , Soonyoung Lee This is my paper
classification cs.AI
keywords PCB routingengine-grounded agentsdesign rule checkreinforcement learningtool-using LLMszero-shot transferbenchmark environmentgeometric feasibility reasoning
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper tries to establish that the right interface determines whether learning-based PCB routing can compete with industry routers. It claims that agents routing a board through an EDA engine's native operations, with the engine's design-rule check after every step, outperform grid-action reinforcement learning and open-loop LLM generation. A compact PPO policy trained only on synthetic boards transfers zero-shot to real open-source boards, reaching a clean-pass rate of 0.86 versus 0.80 for the strongest rule-based router on small boards (0.94 when the engine auto-complete action is removed). Interactive LLM agents that observe each intermediate board also beat plan-and-execute and engine-free modes on clean pass and routing quality. A sympathetic reader would care because it suggests engine-grounded interaction, not bigger models or finer grids, is the bottleneck to clear for automated PCB design.

Core claim

The central claim is that an agent's action space should be the EDA engine's native routing operations, not a cell grid or whole-artifact code generation. The paper builds PCBWorld on the open-source KiCad engine, exposing 58 step-level APIs, and formulates PCB routing as an MDP whose reward is a potential that heavily penalizes design-rule violations. Trained from scratch on synthetic boards, a small Transformer PPO policy achieves Clean Pass 0.86 on 99 small real boards (versus 0.80 for the strongest rule-based baseline) and the authors report 0.94 without the finish action. On medium real boards the same policy trails the rule-based router, and all tested LLM agents score 0 on that split,

What carries the argument

The load-bearing mechanism is the engine-grounded closed loop: every agent action is executed by the EDA engine's native PNS router, and the resulting board state plus DRC feedback re-enter the observation. The reward is a potential Φ(s)=-(f_drv(s)+λ_w·wirelength+λ_v·vias), where f_drv is a concave log penalty counting DRC violations per net, so dense per-step rewards telescope to the terminal reward and share the same optimal policy. On the policy side, a Transformer with an autoregressive pointer head selects coordinates from an engine-provided candidate set, keeping every action syntactically valid and within the engine's routing state machine.

Load-bearing premise

The evaluation assumes that converting each real board into the engine's format faithfully preserves the board's true design rules; the authors relax several DRC checks and, for boards storing no explicit clearance, set the clearance to the minimum spacing found in the board's own reference routing, which makes the reference clean by construction.

What would settle it

Re-run the D3-A and D3-B evaluations with the original, unrelaxed design-rule checks and with no clearance imputed from reference routing; if a synthetic-trained policy's Clean Pass no longer beats or approaches the strongest rule-based router, the zero-shot transfer claim rests on the relaxed evaluator rather than on the learned policy.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • A synthetic-only-trained PPO transfers zero-shot to real small boards, outperforming the strongest rule-based router on Clean Pass (0.86 vs 0.80) and matching it on in-distribution synthetic boards.
  • Interactive tool-using LLM agents that observe intermediate board states beat plan-and-execute and engine-free generation on Clean Pass and potential gain, across all tested models.
  • Removing the engine's auto-complete action from the RL agent's action space improves small-board Clean Pass to 0.94, showing the learned policy, not engine assistance, produces feasible routing.
  • Grid-action RL collapses at finer grid resolutions while API-action PPO stays near perfect, because the decision horizon tracks routed segments rather than cells.
  • Medium real boards remain unsolved: PPO trails the rule-based router and every LLM agent achieves zero Clean Pass on the 10-board medium subset.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If engine-grounded interaction is the right interface, RL-fine-tuned LLMs on the same environment are the obvious next step; the paper's own compact policy already hints the ceiling is higher than one-shot or open-loop prompting.
  • The benchmark's method-agnostic evaluator could double as a general test of geometric feasibility reasoning for tool-use agents beyond PCB routing, since analogous EDA tasks like placement and schematic layout share the same closed-loop structure.
  • Because the real-board evaluation relaxes several DRC checks and imputes missing clearances from each board's own reference routing, the reported clean-pass numbers are an upper bound on true manufacturability; feeding the routed boards through a stricter manufacturing rule set would test the gap directly.
  • The strong zero-shot transfer at small scale suggests synthetic generators tuned to produce harder, denser boards could extend the approach to medium boards without needing real-board training data.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper introduces PCBWorld, a KiCad-based engine-grounded environment for PCB routing, together with PCBWorld-Bench, a benchmark with two synthetic generators (D1, D2) and 679 real open-source boards (D3), scored by eight engine-checked metrics. Agents act through 58 KiCad APIs in a closed loop with DRC feedback; wrappers support both RL (PPO/GRPO) and tool-using LLM agents. The main empirical claims are: (i) the KiCad-API action interface outperforms grid-action RL at fine grid resolutions; (ii) interactive LLM routing beats plan-and-execute and engine-free LLM generation; and (iii) a compact PPO policy trained only on synthetic D2 transfers zero-shot to D3-A, reaching Clean Pass 0.86 vs Freerouting's 0.80 and 0.94 without the finish action, thereby 'approaching a rule-based router refined over decades' (§7). On D3-B, Freerouting remains superior, and LLM agents fail entirely.

Significance. If the empirical claims hold, this is a useful step for learning-based PCB routing: it replaces grid abstractions with native-engine operations, provides a method-agnostic engine-checked evaluator, and demonstrates that engine-grounded interaction helps both RL and LLM agents. The strengths I want to credit explicitly: the environment and benchmark are open-source with transparent API catalogs (Appendix C), the dataset pipeline is described in datasheet form (Appendix O), the reward-shaping equivalence is argued from potential-based shaping (§3.2), and the paper includes useful ablations (reward density, finish removal, engine-engagement level, reward-weight controllability). The main empirical comparison is reproducible in principle, and the seed-level standard deviations are reported in Appendix L. However, the real-board transfer claim rests on the D3 design-rule reconstruction, which is the weakest load-bearing point and needs additional evidence before the headline conclusion is accepted.

major comments (3)
  1. [Appendix O.4 / Table 3] The D3 evaluation depends on the KiCad-9 reconstruction of each board's original design rules. Appendix O.4 states that the compatibility pass relaxes annular width, copper-edge clearance, hole clearance, and non-routing checks, and that 'when a board stores no explicit clearance value, the clearance is instead set to the minimum spacing observed among its own routed traces.' This makes the reference solution clean by construction and scores all methods against potentially looser rules than the source board's true manufacturing rules. The load-bearing D3-A numbers in Table 3 (PPO CP 0.86 vs Freerouting 0.80, PPO w/o finish 0.94) and the §7 'approaching rule-based routers' claim therefore may be inflated. The paper does not report how many of the evaluated D3-A/D3-B boards lack explicit clearance, how the inferred clearance compares with the original rule, or whether PPO's traces exploit
  2. [§3.2 vs §4.3] The potential Φ used to train the RL policy is also the benchmark's Pot. metric and the criterion for best-of-five rollout selection. Specifically, §3.2 defines the reward as Φ(s_T) − Φ(s_0), and §4.3 defines Pot. as ΔΦ and selects the rollout maximizing ΔΦ. Thus PPO is trained and selected on the same objective it is later scored with, which makes its Pot. and selected-rollout CP partly an alignment effect rather than an independent quality measure. This does not invalidate CP as an engine-checked threshold, but it should be disclosed and controlled: report rollouts selected on an independent criterion (e.g., wirelength/vias or a separately defined potential) and move the @1 results of Appendix L, Table 22, into the main comparison.
  3. [Table 3 / Appendix L, Table 21] The central transfer comparison on D3-A rests on a small margin (PPO CP 0.86 ± 0.03 vs Freerouting 0.80 ± 0.01 over 4 seeds). No statistical test or board-level paired comparison is reported, and the D3-B subset contains only 10 boards. Given that the D3-B conclusion (Freerouting beats PPO on larger boards) and the D3-A conclusion (PPO beats Freerouting) are both drawn from these numbers, the authors should report confidence intervals or paired tests and state how many D3-A boards drive the margin. This is not a request for a new experimental family, but the current reporting is too thin for a headline quantitative claim.
minor comments (5)
  1. [§4.3] The definition of CP is clear, but the relationship between the '38 checks' mentioned in the reward paragraph, the 28 routing-relevant codes in Appendix F, and the 35 stock error-level checks is confusing. Please reconcile the counts explicitly in one place.
  2. [Appendix O.5] The D3-B evaluation subset of 10 boards is deterministic and documented, but the choice of 'lower-median board of each bin' deserves a sentence on robustness: a single quantile choice can change the reported CP/Pot. substantially. Since only 10 boards are used, a small sensitivity to the selection rule would strengthen the claim.
  3. [Figure 6 / Table 23] The D1 result is strong, but the warped vertical axis in Figure 6 makes small differences at the top of the range hard to read. The underlying Table 23 with exact values is more informative; consider presenting the table in the main text or making the axis distortion clearer.
  4. [Appendix H.1 / M.1] The LLM prompt includes very detailed routing guidelines, including a specific layer-change detour pattern. Since the same prompt is used across all LLM models, this is fair, but the paper should note explicitly that prompt engineering is part of the evaluated method and that different prompt designs could change the interactive-vs-open-loop ranking.
  5. [Appendix K.4 / K.5] The D1 training-curve endpoints and display clipping are documented, which is good. However, the phrase 'cropped axes' in Table 17 could mislead readers into thinking the final reported routability values are clipped; please reword to clarify that clipping applies only to diagnostic validation plots.

Circularity Check

2 steps flagged

D3 evaluation clearance is read off each board's own reference routing, making the reference clean by construction; the Pot. metric also equals the RL training potential ΔΦ.

specific steps
  1. self definitional [Appendix O.4 (Preprocessing); §4.2 (D3 dataset); Table 3 Reference row]
    "KiCad-9 floor constraints for annular width, copper-edge clearance, and hole clearance are relaxed to match earlier-version board compatibility. ... when a board stores no explicit clearance value, the clearance is instead set to the minimum spacing observed among its own routed traces. — §4.2: retain only boards that remain fully connected and DRV-free after conversion."

    For each no-explicit-clearance D3 board, the evaluation clearance is defined as the minimum spacing measured in that board's own reference routing. The reference's traces therefore satisfy the clearance rule by definition, and its DRV-free status (the §4.2 retention filter behind the Reference CP=1.00 in Table 3) is guaranteed by construction, not demonstrated. The rule that certifies the reference is read off the reference itself, while O.4 also relaxes annular-width, copper-edge, and hole-clearance floors in the same pass, so the claim that D3 preserves the boards' own 'design-rule settings' is self-referential for these boards. All zero-shot D3-A/D3-B CP numbers in Table 3 are scored under this bar, and the paper does not report how many D3-A boards lack explicit clearance; looser-than-

  2. self definitional [§3.2 (Reward); §4.3 and Appendix I (Evaluation Metrics)]
    "we define a potential function Φ(𝑠) that measures the board quality, Φ(𝑠)=−[𝑓drv(𝑠)+𝜆𝑤ℓ(𝑠)+𝜆𝑣𝑛via(𝑠)] ... The MDP's reward is the terminal reward ... 𝑟𝑇 =Φ(𝑠𝑇)−Φ(𝑠0) at termination. — Appendix I: Potential Gain (Pot.↑). Our central routing-quality measure is the potential gain from the bare-board state ... ΔΦ(𝑠𝑏,𝑖)=Φ(𝑠𝑏,𝑖)−Φ(𝑠𝑏,0)."

    The RL policies (PPO, GRPO, PPO-terminal) are trained to maximize Φ, since the per-step reward telescopes to r_T = Φ(s_T) − Φ(s_0), and the benchmark's Pot. metric is defined as exactly this same ΔΦ. Moreover, the @5 protocol selects each board's single rollout as 'the rollout with the largest potential gain' (Appendix I), so RL's Pot. score and its best-of-five selection are taken on the agent's own training objective, while the LLM and rule-based rows are scored on a potential they do not optimize. The identity Pot. = RL reward holds by construction; it is bounded (CP is the primary, engine-checked metric, and Freerouting still leads Pot. on D3-A), but the RL rows' Pot. comparisons and rollout selection are self-referential.

full rationale

The paper's central comparative claims are not derived from the benchmark's own definitions: (i) the D1 grid-scale result (PPO keeps routability at grid resolutions where A2C and Sable collapse) is an empirical scaling comparison on matched instances; (ii) the interactive > plan-and-execute > engine-free ordering for LLM agents is measured on engine-checked CP/DRV with a stated mechanism (closed-loop engine feedback); (iii) the D2→D3 zero-shot transfer is a genuine train-on-synthetic/evaluate-on-real protocol. There are essentially no author self-citations; references to Jumanji, Sable, PCBench, Freerouting, KiCad, and Ng et al.'s potential-based shaping are external and correct, and the shaping equivalence is a standard theorem, not a load-bearing self-citation. Two genuinely self-referential constructions do exist. First (the load-bearing one): Appendix O.4 relaxes DRC floors and, for boards storing no explicit clearance, defines the evaluation clearance as the minimum spacing in that board's own reference routing. This makes the reference clean by construction, guarantees the 'fully connected and DRV-free' retention filter for those boards, and sets the Reference CP=1.00 tautologically; all zero-shot D3 CP numbers are scored under this self-referential bar, and the paper does not quantify how many evaluation boards lack explicit clearance. The methods-vs-methods comparison still uses one common evaluator, so PPO's 0.86-vs-Freerouting 0.80 margin is not forced by the construction, but the absolute level and the 'approaches a rule-based router refined over decades' claim rest on a rule partly read off the reference. Second (minor): the Pot. metric is literally the ΔΦ that RL optimizes, and @5 selection uses the same ΔΦ, so RL's secondary metric and rollout choice are its own training objective; this is disclosed and does not force the headline ordering (Freerouting beats PPO on D3-A Pot.). Overall: partial circularity — the reference-clean claim and the Pot. metric reduce by construction, while the core interaction and transfer comparisons retain independent empirical content; the honest score is 5, not higher, because no step forces the headline relative outcome and the circular construction is documented in the manuscript itself.

Axiom & Free-Parameter Ledger

4 free parameters · 7 axioms · 0 invented entities

No new physical entities are postulated; the novel objects here are software artifacts (the nested state dictionary, token streams, benchmark datasets), not new forces, particles, dimensions, or conserved quantities. The free parameters are the reward-shaping constants and the D3 clearance heuristic; the axioms are dominated by domain assumptions about KiCad as a ground-truth router/checker and about synthetic-to-real transfer.

free parameters (4)
  • reward weights λ_w, λ_v = λ_w = 0.002, λ_v = 0.1 (default)
    Hand-chosen trade-off between wirelength and via count in the potential Φ; reported PPO policies are trained with these defaults (Appendix G, Table 15). A 3×3 sweep shows controllability, but the main results depend on the default choice.
  • DRC penalty hyperparameters (s_agg, s_pn, o) = (3, 1, 2)
    Chosen shape of the concave DRV penalty in Eq. (3) (Appendix G); sets the breadth-vs-depth 3:1 weighting and the log-knee offset that defines the training signal near zero DRVs.
  • D3 default clearance = min spacing among the board's own routed traces (when no explicit clearance stored)
    Appendix O.4: for boards without an explicit clearance value the benchmark sets clearance to the minimum spacing observed in the reference routing, so DRC feasibility is defined by the reference geometry itself.
  • LLM step budget T = 200
    Per-episode step limit for LLM agents (Appendix M.1); affects whether LLM agents can complete boards. The RL horizon is 256 (Table 15).
axioms (7)
  • domain assumption KiCad's PNS router and DRC engine correctly implement PCB routing semantics and error detection.
    The environment's validity rests on the unmodified C++ engine (L1, Appendix B); agent actions are executed and scored by the engine without Python-side verification.
  • domain assumption The 38 error-level DRC checks (35 stock errors plus DANGLING_VIA/DANGLING_TRACK/NET_CONFLICT promoted from warnings) are an adequate geometric-feasibility criterion.
    Appendix F defines the counting convention used for both reward and evaluation; the promotion of three warning codes is the authors' modeling choice.
  • domain assumption Relaxing non-routing and floor DRC checks in the D3 compatibility pass preserves the boards' true design intent.
    Appendix O.4: annular width, copper-edge clearance, and hole clearance constraints are relaxed to KiCad-9 compatibility; if these are genuine manufacturing rules, the evaluation is permissive.
  • ad hoc to paper The minimum-spacing clearance proxy recovers the intended design rule for boards with no explicit clearance.
    Appendix O.4: clearance is set from reference-trace spacing; no independent evidence that this equals the board's original rule.
  • domain assumption Synthetic D2 gridless boards are a sufficient training distribution for zero-shot transfer to D3 real boards.
    The central transfer claim assumes D2 difficulty/geometry (4-6 nets, 8-21 pads, 2 layers) overlaps D3-A; the paper itself notes the limit on larger D3-B boards.
  • standard math Potential-based reward shaping equivalence (per-step vs terminal reward) holds at γ=0.995.
    §3.2 invokes Ng et al. [40]; Appendix K.2 notes the telescoping holds 'approximately' because training uses γ=0.995, not 1.
  • domain assumption The engine-provided candidate-point discretization does not exclude near-optimal routes.
    §3.2/H.2: RL selects only from pad centers, track/via endpoints, and an 8-way 0.5 mm offset grid; this restricts the RL policy's reachable geometry.

pith-pipeline@v1.3.0-alltime-deepseek · 47679 in / 18584 out tokens · 168144 ms · 2026-08-04T04:27:05.339551+00:00 · methodology

0 comments
read the original abstract

PCB routing is the task of connecting the nets of a board with copper traces under strict design rules, yet learning-based methods still lag behind rule-based routers. We introduce PCBWorld, an open-source engine-grounded PCB routing environment built on KiCad, an electronic design automation (EDA) engine. As a human engineer does, agents in PCBWorld interactively route a board through the engine's native operations, guided by its Design Rule Check (DRC) feedback. The environment supports both RL and tool-using LLM agents. Alongside the environment, PCBWorld-Bench provides three board datasets in the native .kicad_pcb format, two controllable synthetic generators and 679 real open-source boards. It scores any completed board with eight engine-checked evaluation metrics, regardless of the routing method. In our experiments, agents in PCBWorld consistently outperformed grid-action RL policies and open-loop LLM baselines, and an RL policy trained only on synthetic boards transferred zero-shot to real boards, approaching rule-based routers.

Figures

Figures reproduced from arXiv: 2607.05915 by Han-Seul Jeong, HyungSeok Song, Junseok Park, Seohui Bae, Soonyoung Lee, Won-Seok Choi, Youngjoon Park.

Figure 2
Figure 2. Figure 2: Core concepts of PCB routing. Pads belonging to the [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 1
Figure 1. Figure 1: Overview of PCBWorld and PCBWorld-Bench. Agents invoke the KiCad engine’s native API and condition each step on engine-computed feedback. this limit [5, 38], but unlike in language, vision, and games, they are not yet competitive even with rule-based routers. We attribute this limitation to how the routing problem is mod￾eled. Existing RL formulations either cast routing as cell-by-cell movement on a grid,… view at source ↗
Figure 3
Figure 3. Figure 3: Two Gym wrappers communicate with the shared engine through a unified state dictionary, which they re-encode [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Example Action of PCBWorld. An example of make_line, where the routing_mode argument alters routing behavior through the KiCad routing engine, resulting in substantially different trace geometries across walkaround, push_n_shove, and mark_as_obstacles. reuse those of Equation (1), and 𝑓𝑑 is a monotone-increasing, con￾cave penalty that assigns a large marginal cost to the first violation on each net. On PCB… view at source ↗
Figure 3
Figure 3. Figure 3: Gym Wrappers. Two Gym wrappers communicate with the shared engine through a unified state dictionary, which [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 5
Figure 5. Figure 5: Example boards from PCBWorld-Bench. Repre￾sentative examples from the three board types, synthetic grid-based boards (D1), synthetic gridless boards (D2), and real-world open-source boards (D3). can add new .kicad_pcb boards as evaluation instances or define new metrics from any quantity the KiCad engine can compute. 4.2 Board Datasets [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Simulation Results of Synthetic Grid-based Boards [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗
Figure 6
Figure 6. Figure 6: Simulation Results of Synthetic Grid-based Boards [PITH_FULL_IMAGE:figures/full_fig_p005_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Engine engagement in the LLM agent across interactive, plan-only, and engine-free modes. Table 20 in Appendix L [PITH_FULL_IMAGE:figures/full_fig_p007_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Examples of routed boards (D3-A). Wire traces in different colors (red and blue) represent wire segments on distinct [PITH_FULL_IMAGE:figures/full_fig_p009_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Reward weight sweep (3×3 factorial). Bars show marginal means with error bars. Wirelength: left axis (or￾ange); via count: right axis (teal). robustness by accumulating the model’s intermediate thoughts, but also enables explainable reasoning behind the final action. In prac￾tice, by analyzing the model’s <think></think> blocks in routing tasks with PCBWorld, we identify several key observations, which are… view at source ↗
Figure 8
Figure 8. Figure 8: Engine engagement in the LLM agent on D2 and D3-A across interactive, plan-and-execute, and engine-free modes. [PITH_FULL_IMAGE:figures/full_fig_p007_8.png] view at source ↗
Figure 10
Figure 10. Figure 10: PCBWorld architecture. A reinforcement-learning view of the proposed environment. Three policy classes, a rule-based router as a deterministic baseline, an RL Agent built on a from-scratch Transformer, and an LLM Agent that issues tool calls, share a single Gymnasium environment through the standard action 𝑎𝑡 and the state 𝑠𝑡 , reward 𝑟𝑡 signals. Inside the environment, our contribution spans L4 (the Gymn… view at source ↗
Figure 9
Figure 9. Figure 9: Reward weight sweep (3×3 factorial). Bars show marginal means with error bars. Wirelength: left axis (or￾ange); via count: right axis (teal). Controllability through penalty weights. We test whether the policy responds to fine-grained routing objectives by sweeping the wirelength weight 𝜆𝑤 ∈ {0, 0.001, 0.002} and the via weight 𝜆𝑣 ∈ {0, 0.05, 0.1} in a 3×3 factorial design ( [PITH_FULL_IMAGE:figures/full_… view at source ↗
Figure 11
Figure 11. Figure 11: Virtual move versus physical commit. Within a routing session, [PITH_FULL_IMAGE:figures/full_fig_p016_11.png] view at source ↗
Figure 10
Figure 10. Figure 10: PCBWorld architecture. A reinforcement-learning view of the proposed environment. Three classes of routing methods, a scripted rule-based baseline, an RL agent built on a from-scratch Transformer, and an LLM agent that issues tool calls, share a single Gymnasium environment through the standard action 𝑎𝑡 and the state 𝑠𝑡 , reward 𝑟𝑡 signals. Inside the environment, our contribution spans L4 (the Gymnasium… view at source ↗
Figure 12
Figure 12. Figure 12: Session termination modes. Three distinct primitives close an open routing session. [PITH_FULL_IMAGE:figures/full_fig_p017_12.png] view at source ↗
Figure 11
Figure 11. Figure 11: Virtual move versus physical commit. Within a routing session, [PITH_FULL_IMAGE:figures/full_fig_p014_11.png] view at source ↗
Figure 13
Figure 13. Figure 13: Corner posture control. When two endpoints are joined by an L-shape, the router must choose between leaving the [PITH_FULL_IMAGE:figures/full_fig_p017_13.png] view at source ↗
Figure 12
Figure 12. Figure 12: Session termination modes. Three distinct primitives close an open routing session. [PITH_FULL_IMAGE:figures/full_fig_p014_12.png] view at source ↗
Figure 14
Figure 14. Figure 14: Via placement and layer transition. In a multilayer board, electrical connections between different layers are mediated [PITH_FULL_IMAGE:figures/full_fig_p017_14.png] view at source ↗
Figure 13
Figure 13. Figure 13: Corner posture control. When two endpoints are joined by an L-shape, the PNS router must choose between leaving [PITH_FULL_IMAGE:figures/full_fig_p015_13.png] view at source ↗
Figure 15
Figure 15. Figure 15: Obstacle interaction policies. set_routing_mode chooses one of three policies for interacting with existing copper. MarkObstacles performs collision detection and aborts trace generation when a clearance constraint would be violated. Shove pushes neighbouring tracks aside to dynamically clear space for the new path. Walkaround preserves the existing copper geometry and searches for an optimal detour aroun… view at source ↗
Figure 14
Figure 14. Figure 14: Via placement and layer transition. In a multilayer board, electrical connections between different layers are mediated [PITH_FULL_IMAGE:figures/full_fig_p015_14.png] view at source ↗
Figure 16
Figure 16. Figure 16: Trace corner geometry. set_corner_mode controls the angular format at trace corners. The industry-standard 45◦ miter, MITERED_45, is optimized to minimize signal loss and avoid manufacturing defects. The 90◦ rectilinear corner, MITERED_ 90, is reserved for cases that require special geometric alignment [PITH_FULL_IMAGE:figures/full_fig_p018_16.png] view at source ↗
Figure 15
Figure 15. Figure 15: Obstacle interaction policies. set_routing_mode chooses one of three policies for interacting with existing copper. mark_as_obstacles performs collision detection and aborts trace generation when a clearance constraint would be violated. push_n_shove pushes neighboring tracks aside to dynamically clear space for the new path. walkaround preserves the existing copper geometry and searches for an optimal de… view at source ↗
Figure 17
Figure 17. Figure 17: Trace width control. set_track_width explicitly sets the physical conductor width. Width is the key parameter that determines characteristic impedance and current-carrying capacity, distinguishing wide power traces that carry large currents from thin signal traces that carry fine signals. F Design Rule Check Catalog F.1 DRC Catalog and Severity Mapping Source of truth. KiCad enumerates every Design Rule C… view at source ↗
Figure 16
Figure 16. Figure 16: Trace corner geometry. set_corner_mode controls the angular format at trace corners. The industry-standard 45◦ miter, MITERED_45, is optimized to minimize signal loss and avoid manufacturing defects. The 90◦ rectilinear corner, MITERED_ 90, is reserved for cases that require special geometric alignment. 15 [PITH_FULL_IMAGE:figures/full_fig_p015_16.png] view at source ↗
Figure 18
Figure 18. Figure 18: Via geometry and reset. The outer diameter and inner drill of a via are adjusted individually and independently of [PITH_FULL_IMAGE:figures/full_fig_p019_18.png] view at source ↗
Figure 17
Figure 17. Figure 17: Trace width control. set_track_width explicitly sets the physical conductor width. Width is the key parameter that determines characteristic impedance and current-carrying capacity, distinguishing wide power traces that carry large currents from thin signal traces that carry fine signals [PITH_FULL_IMAGE:figures/full_fig_p016_17.png] view at source ↗
Figure 19
Figure 19. Figure 19: Trace drag-to-modify. Pulling the midpoint of an already committed trace allows its geometry to be reshaped flexibly. [PITH_FULL_IMAGE:figures/full_fig_p019_19.png] view at source ↗
Figure 18
Figure 18. Figure 18: Via geometry and reset. The outer diameter and inner drill of a via are adjusted individually and independently of [PITH_FULL_IMAGE:figures/full_fig_p016_18.png] view at source ↗
Figure 20
Figure 20. Figure 20: Track deletion methods. A track object can be identified and removed by two complementary logical approaches. [PITH_FULL_IMAGE:figures/full_fig_p019_20.png] view at source ↗
Figure 19
Figure 19. Figure 19: Trace drag-to-modify. Pulling the midpoint of an already committed trace allows its geometry to be reshaped flexibly. [PITH_FULL_IMAGE:figures/full_fig_p016_19.png] view at source ↗
Figure 21
Figure 21. Figure 21: Via deletion methods. By the same logic as track removal, the vertical connection object is selectively removed either [PITH_FULL_IMAGE:figures/full_fig_p020_21.png] view at source ↗
Figure 20
Figure 20. Figure 20: Track deletion methods. A track object can be identified and removed by two complementary logical approaches. [PITH_FULL_IMAGE:figures/full_fig_p017_20.png] view at source ↗
Figure 22
Figure 22. Figure 22: D1 grid-size scalability training-time validation diagnostics. Columns separate PPO, Jumanji A2C, and SABLE runs; [PITH_FULL_IMAGE:figures/full_fig_p029_22.png] view at source ↗
Figure 21
Figure 21. Figure 21: Via deletion methods. By the same logic as track removal, the vertical connection object is selectively removed either [PITH_FULL_IMAGE:figures/full_fig_p017_21.png] view at source ↗
Figure 23
Figure 23. Figure 23: PPO/GRPO training-time validation diagnostics. Columns correspond to PPO, GRPO, and PPO (terminal); rows show [PITH_FULL_IMAGE:figures/full_fig_p033_23.png] view at source ↗
Figure 22
Figure 22. Figure 22: D1 grid-size scalability training-time validation diagnostics. Columns separate PPO, A2C (Jumanji), and Sable runs; [PITH_FULL_IMAGE:figures/full_fig_p028_22.png] view at source ↗
Figure 24
Figure 24. Figure 24: Full prompt template for the PCBWorld agent. M.2 Baselines Engine-free (open-loop) generation. An LLM directly generates a complete KiCad board file (.kicad_pcb) from the initial board state. You are an expert PCB routing engineer using KiCad PCB format. Your task is to generate valid PCB routing (tracks and vias) for a given KiCad PCB board. ## Instructions - Analyze the given PCB layout, including compo… view at source ↗
Figure 25
Figure 25. Figure 25: Full prompt template for the engine-free (open-loop) generation. [PITH_FULL_IMAGE:figures/full_fig_p036_25.png] view at source ↗
Figure 26
Figure 26. Figure 26: Full prompt template for the plan-only (open-loop) generation. [PITH_FULL_IMAGE:figures/full_fig_p038_26.png] view at source ↗
Figure 27
Figure 27. Figure 27: Case Study 1 (0018_hy_adapter). In our current action design, determining the routing priority of nets is critically important. Although different nets were selected for different reasons, we observe that routing succeeds when a particular net (net 3) is selected first, whereas it fails when another net (net 4) is selected first. 39 [PITH_FULL_IMAGE:figures/full_fig_p039_27.png] view at source ↗
Figure 28
Figure 28. Figure 28: Case Study 2 (0100_smt-zvs-driver_IH10-mc). Failure case (top) and success case (bottom). Since the action space does not include direct editing of pre-existing tracks, once congestion is encountered, the agent repeatedly attempts rerouting through alternative paths. In contrast, proactively anticipating congestion and initiating routing from a different region enables more effective routing with fewer st… view at source ↗
Figure 27
Figure 27. Figure 27: Examples of routed boards (D3-A). Full version of the main-text Figure 7, showing all three boards. Red and blue [PITH_FULL_IMAGE:figures/full_fig_p038_27.png] view at source ↗
Figure 28
Figure 28. Figure 28: Case Study 1 (0018_hy_adapter). In this action design, determining the routing priority of nets is critically important. Although different nets were selected for different reasons, we observe that routing succeeds when a particular net (net 3) is selected first, whereas it fails when another net (net 4) is selected first. 39 [PITH_FULL_IMAGE:figures/full_fig_p039_28.png] view at source ↗
Figure 29
Figure 29. Figure 29: Case Study 2 (0100_smt-zvs-driver_IH10-mc). Failure case (top) and success case (bottom). Since the action space does not include direct editing of pre-existing tracks, once congestion is encountered, the agent repeatedly attempts rerouting through alternative paths. In contrast, proactively anticipating congestion and initiating routing from a different region enables more effective routing with fewer st… view at source ↗
Figure 30
Figure 30. Figure 30: Pad-count distribution of the 679 curated D3 boards, stacked by split (log-scaled horizontal axis). The dashed line [PITH_FULL_IMAGE:figures/full_fig_p042_30.png] view at source ↗
Figure 31
Figure 31. Figure 31: Pad-count distribution of the two-layer D3-B and D3-C pools from which the evaluation subsets are drawn, with the [PITH_FULL_IMAGE:figures/full_fig_p043_31.png] view at source ↗

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    Anything else is forbidden

    dx == -dy (and both nonzero) (NW / SE -- 135, diagonal) Equivalently, every segment is horizontal, vertical, or a 45-degree diagonal where |dx| == |dy|. Anything else is forbidden. 35 KDD Workshop on Agentic AI ’26, August 9–13, 2026, Jeju, Republic of Korea Song et al. ### How to handle non-octilinear paths If the natural route between two pads is at an ...

    2026

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    36 PCBWorld: A Benchmark Environment for Engine-Grounded PCB Design Automation KDD Workshop on Agentic AI ’26, August 9–13, 2026, Jeju, Republic of Korea

    If the first pad has tag`1`-> use 1. 36 PCBWorld: A Benchmark Environment for Engine-Grounded PCB Design Automation KDD Workshop on Agentic AI ’26, August 9–13, 2026, Jeju, Republic of Korea

    2026

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    If the first pad has tag`2`-> use 2

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    (This avoids an unnecessary via.)

    If the first pad has tag`th`and at least one other pad of this net has tag`1`or`2`-> use that other pad's layer. (This avoids an unnecessary via.)

Showing first 80 references.