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ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA

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arxiv 2505.02016 v1 pith:PDM5LBUU submitted 2025-05-04 cs.AR

classification cs.AR
keywords forgeedacomprehensiveperformancecircuitdatasetnetliststasksability
verification ladder T0 review T1 audit T2 compute T3 formal
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We introduce ForgeEDA, an open-source comprehensive circuit dataset across various categories. ForgeEDA includes diverse circuit representations such as Register Transfer Level (RTL) code, Post-mapping (PM) netlists, And-Inverter Graphs (AIGs), and placed netlists, enabling comprehensive analysis and development. We demonstrate ForgeEDA's utility by benchmarking state-of-the-art EDA algorithms on critical tasks such as Power, Performance, and Area (PPA) optimization, highlighting its ability to expose performance gaps and drive advancements. Additionally, ForgeEDA's scale and diversity facilitate the training of AI models for EDA tasks, demonstrating its potential to improve model performance and generalization. By addressing limitations in existing datasets, ForgeEDA aims to catalyze breakthroughs in modern IC design and support the next generation of innovations in EDA.

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Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Miter-Aware LUT Mapping: Aligning Structure and Solvability for Efficient Logic Equivalence Checking

    cs.AR 2026-07 conditional novelty 6.0 of 10

    Joint LUT mapping of golden and implementation circuits, combined with Gaussian-guided XOR modeling and solver-oriented LUT selection, reduces SAT-based logic equivalence checking runtime by up to 92.1%.

  2. DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learning

    cs.LG 2025-02 conditional novelty 6.0 of 10

    DeepCell fuses AIG and post-mapping netlist views with masked autoencoding, achieving 2.77% lower ECO patch cost and 15-16% lower area-delay product in technology mapping.

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