DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation | Paper Citation Record

Observation d5f60d4a-ccc1-4ad3-8b1d-0075459c4326 · outbound

This paper cites Interconnect Design for Heterogeneous Integration of Chiplets in the AMD Instinct MI300X Accelerator,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Interconnect Design for Heterogeneous Integration of Chiplets in the AMD Instinct MI300X Accelerator,

Reference 1

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:50.800143Z

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Observation 6946c327-798a-4675-99de-d345cb0e55a7 · outbound

This paper cites Enabling Scalable Chiplet-Based Uniform Memory Architectures with Silicon Photonics,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Enabling Scalable Chiplet-Based Uniform Memory Architectures with Silicon Photonics,

Reference 2

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Observation 73337122-ebae-4ec1-8840-788d1383b3be · outbound

This paper cites Pioneering Chiplet Technology and Design for the AMD EPYC and Ryzen Processor Families: Industrial Product,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Pioneering Chiplet Technology and Design for the AMD EPYC and Ryzen Processor Families: Industrial Product,

Reference 3

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Observation facbb6dd-754e-4e4e-b935-fa97e1a5d8d4 · outbound

This paper cites Active Interposer Technology for Chiplet- Based Advanced 3D System Architectures,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Active Interposer Technology for Chiplet- Based Advanced 3D System Architectures,

Reference 4

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Observation dd2d4360-ee83-44c4-beba-9fde099c69f0 · outbound

This paper cites Coherence Attacks and Countermeasures in Interposer- Based Chiplet Systems,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Coherence Attacks and Countermeasures in Interposer- Based Chiplet Systems,

Reference 5

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:50.999169Z

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Observation ac296e22-943a-4da0-a482-8863f7f9567e · outbound

This paper cites AMD Next-Generation “Zen 4.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation AMD Next-Generation “Zen 4

Reference 6

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.101247Z

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Observation 3d871dd8-3377-4abc-b1f0-2bf1c6ce5ae5 · outbound

This paper cites Accelerating Innovation Through a Standard Chiplet Inter- face: The Advanced Interface Bus (AIB),.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Accelerating Innovation Through a Standard Chiplet Inter- face: The Advanced Interface Bus (AIB),

Reference 7

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Observation 1a1f5ee8-9a6b-408d-aba7-dcabb1a5342d · outbound

This paper cites Universal Chiplet Interconnect Express (UCIe): An Open Industry Standard for Innovations With Chiplets at Package Level,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Universal Chiplet Interconnect Express (UCIe): An Open Industry Standard for Innovations With Chiplets at Package Level,

Reference 8

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.240495Z

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Observation e6a34b72-e86f-4889-8bdb-2ca58a9b714d · outbound

This paper cites Analysis of UCIe 48/64 GT/s Electrical Links,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Analysis of UCIe 48/64 GT/s Electrical Links,

Reference 9

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.245040Z

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Observation f6568694-529b-4194-a9ba-52d2e5b27479 · outbound

This paper cites Chapter 2: High Performance Computing (HPC),.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Chapter 2: High Performance Computing (HPC),

Reference 10

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Observation 065c781a-830f-45b9-a9f2-f5f6e27bb905 · outbound

This paper cites The Road to 64G UCIe IP: What Designers Need to Know,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation The Road to 64G UCIe IP: What Designers Need to Know,

Reference 11

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.254575Z

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Observation a3a69456-f5f3-423d-a69f-8bd2cfb5e671 · outbound

This paper cites Kite: A Family of Heterogeneous Interposer Topologies Enabled via Accurate Inter- connect Modeling,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Kite: A Family of Heterogeneous Interposer Topologies Enabled via Accurate Inter- connect Modeling,

Reference 12

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.259208Z

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Observation d4f49d40-6a98-4ef8-8f74-e31f9ae7f595 · outbound

This paper cites The gem5 Simulator: Version 20.0+.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation The gem5 Simulator: Version 20.0+

Reference 13

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.264193Z

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Observation 3c410598-28f0-46ec-b3b0-5d662edce955 · outbound

This paper cites an unresolved cited work.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Unresolved cited work

Reference 14

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Observation e23daaaf-bbfc-4bcf-8d7e-d335c14d05eb · outbound

This paper cites Quasi-Cyclic LDPC Codes for Fast Encoding,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Quasi-Cyclic LDPC Codes for Fast Encoding,

Reference 15

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Observation 2a61ea8e-08a7-4005-b5f7-b58e2856b057 · outbound

This paper cites LDPC- in-SSD: Making Advanced Error Correction Codes Work Effectively in Solid State Drives,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation LDPC- in-SSD: Making Advanced Error Correction Codes Work Effectively in Solid State Drives,

Reference 16

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.277319Z

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Observation dc72520a-ab9c-430c-8dac-ad77368cd747 · outbound

This paper cites The PCIe 6.0 Specification Webinar Q&A: Error Detection and Correction (FEC),.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation The PCIe 6.0 Specification Webinar Q&A: Error Detection and Correction (FEC),

Reference 17

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.281457Z

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Observation 79e867b6-2d75-4da6-b3d5-c8af542da227 · outbound

This paper cites Low-Density Parity-Check Codes,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Low-Density Parity-Check Codes,

Reference 18

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.286108Z

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Observation 4e7a1fc1-b747-4737-a32e-d2796ebfc108 · outbound

This paper cites GARNET: A Detailed On-Chip Network Model Inside a Full-System Simulator,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation GARNET: A Detailed On-Chip Network Model Inside a Full-System Simulator,

Reference 19

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Observation 17667eae-528a-4469-8090-270baecb36ed · outbound

This paper cites Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-Core Simulation (SC),.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-Core Simulation (SC),

Reference 20

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Observation a996b538-1c31-4468-be4d-61e6211530b8 · outbound

This paper cites DARSIM: A Parallel Cycle-Level NoC Simulator,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation DARSIM: A Parallel Cycle-Level NoC Simulator,

Reference 21

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Observation bf83ea85-5472-446e-9d64-7f1ba0362b0e · outbound

This paper cites A Detailed and Flexible Cycle- Accurate Network-on-Chip Simulator,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation A Detailed and Flexible Cycle- Accurate Network-on-Chip Simulator,

Reference 22

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Observation bec28b90-f115-4772-a40a-23550e2708fd · outbound

This paper cites Noxim: An Open, Extensible and Cycle-Accurate Network on Chip Simulator,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Noxim: An Open, Extensible and Cycle-Accurate Network on Chip Simulator,

Reference 23

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Observation 115f74a9-6430-44da-9919-2c4641091ba9 · outbound

This paper cites Muchisim: A Simulation Framework for Design Exploration of Multi-Chip Many- core Systems,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Muchisim: A Simulation Framework for Design Exploration of Multi-Chip Many- core Systems,

Reference 24

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Observation 0eeaacf8-167e-4d76-a07b-e34f53e9a022 · outbound

This paper cites BZSim: Fast, Large-Scale Mi- croarchitectural Simulation with Detailed Interconnect Modeling,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation BZSim: Fast, Large-Scale Mi- croarchitectural Simulation with Detailed Interconnect Modeling,

Reference 25

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.319393Z

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Observation 8063a344-09d9-4ea9-8030-0a52265835a5 · outbound

This paper cites Evaluating Chiplet-based Large- Scale Interconnection Networks via Cycle-Accurate Packet-Parallel Simulation,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Evaluating Chiplet-based Large- Scale Interconnection Networks via Cycle-Accurate Packet-Parallel Simulation,

Reference 26

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Observation fb9a8be7-77fc-409b-b2e7-19c7a359ae6c · outbound

This paper cites RapidChiplet: A Toolchain for Rapid Design Space Exploration of Inter-Chiplet Interconnects,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation RapidChiplet: A Toolchain for Rapid Design Space Exploration of Inter-Chiplet Interconnects,

Reference 27

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Observation 5518e31f-7d59-46c2-a804-2fd041c4b34a · outbound

This paper cites 32-bit Cyclic Redundancy Codes for Internet Applica- tions,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation 32-bit Cyclic Redundancy Codes for Internet Applica- tions,

Reference 28

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Observation c930a170-8a65-45cc-9c93-bf4b28b9ed64 · outbound

This paper cites Richardson and R.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Richardson and R

Reference 29

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Observation 908ead3d-5d0f-4978-b05d-6c1bc182eafa · outbound

This paper cites Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories,

Reference 30

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Observation 9fcb66b8-6cec-4226-9651-ae68fb4731fb · outbound

This paper cites an unresolved cited work.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Unresolved cited work

Reference 31

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Observation a02d6b40-516b-4622-8c8f-dc2844219136 · outbound

This paper cites Clocking for PCIe Applications.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Clocking for PCIe Applications

Reference 32

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Observation 0e55afd4-0a67-49ed-9783-52fdb8c5a149 · outbound

This paper cites Per- formance Analysis of Bump in Tapered TSV: Impact on Crosstalk and Power Loss,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Per- formance Analysis of Bump in Tapered TSV: Impact on Crosstalk and Power Loss,

Reference 33

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Observation 4c3cd5aa-1d2e-42d1-9669-901b5b441bba · outbound

This paper cites A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5- D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5- D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring,

Reference 34

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Observation f097debc-7ea4-4b44-8e78-80a3519fde95 · outbound

This paper cites Beyond CPO: A Motivation and Approach for Bringing Optics Onto the Silicon Interposer,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Beyond CPO: A Motivation and Approach for Bringing Optics Onto the Silicon Interposer,

Reference 35

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Observation 2f523bbf-1c71-4299-8803-9910b6f5fde1 · outbound

This paper cites Digital Clock and Data Recovery Circuit Design: Challenges and Tradeoffs,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Digital Clock and Data Recovery Circuit Design: Challenges and Tradeoffs,

Reference 36

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Observation 8c66090e-3b80-4a26-8f88-6ffe186b5634 · outbound

This paper cites An Equalizer Adaptation Algorithm to Reduce Jitter in Binary Receivers,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation An Equalizer Adaptation Algorithm to Reduce Jitter in Binary Receivers,

Reference 37

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Observation 68232c9a-1aad-49e8-949d-1bd66d5ebd03 · outbound

This paper cites A Study of BER and EVM Degradation in Digital Modulation Schemes Due to PLL Jitter and Communication- Link Noise,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation A Study of BER and EVM Degradation in Digital Modulation Schemes Due to PLL Jitter and Communication- Link Noise,

Reference 38

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Observation f91b027d-c3e7-4b5d-b167-75eb615ea74d · outbound

This paper cites A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory,

Reference 39

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Observation 0ba0f5a0-2d2f-4372-a8aa-ffc52c53196c · outbound

This paper cites Seamless Transition to PCIe 5.0 Technology in System Implementations Webinar Q&A,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Seamless Transition to PCIe 5.0 Technology in System Implementations Webinar Q&A,

Reference 40

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Observation 915aa9c5-a278-4ef6-92e4-285ca84624ff · outbound

This paper cites Optimized Signal and Power Integrity of Silicon Interposer for HBM2E in CoWoS Packaging,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Optimized Signal and Power Integrity of Silicon Interposer for HBM2E in CoWoS Packaging,

Reference 41

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.394769Z

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Observation decf515e-776d-4942-ac09-e14ef681a14a · outbound

This paper cites High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Appli- cations: Challenges and Solutions,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Appli- cations: Challenges and Solutions,

Reference 42

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Observation 0417fd15-0282-450d-a010-5fa3369a7333 · outbound

This paper cites Achieving Better Chiplet Design Signal Integrity with UCIe,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Achieving Better Chiplet Design Signal Integrity with UCIe,

Reference 43

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Observation ca604dbd-2923-4fbd-9db1-f8f12acdbd05 · outbound

This paper cites UCIe Electrical, Form-Factor, and Compliance,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation UCIe Electrical, Form-Factor, and Compliance,

Reference 44

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Observation 074212f4-8aa8-4ba8-9836-4482dcf6156c · outbound

This paper cites Signal Integrity Design and Analysis of Universal Chiplet Interconnect Express (UCIe) Channel in Silicon Interposer for Advanced Package,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Signal Integrity Design and Analysis of Universal Chiplet Interconnect Express (UCIe) Channel in Silicon Interposer for Advanced Package,

Reference 45

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Observation 3c990a5f-ca15-4602-93c8-18ed9b79df34 · outbound

This paper cites Bit-Interleaved Coded Modula- tion,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Bit-Interleaved Coded Modula- tion,

Reference 46

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Observation db1761b5-9c98-40b9-bb5d-0243e18dd083 · outbound

This paper cites A Reduced Complexity Decoder Architecture via Layered Decoding of LDPC Codes,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation A Reduced Complexity Decoder Architecture via Layered Decoding of LDPC Codes,

Reference 47

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Observation f4460daf-eaf2-42a4-98bf-a21a47b8f353 · outbound

This paper cites UCIe Specification Revision 2.0,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation UCIe Specification Revision 2.0,

Reference 48

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Observation 113f4656-647f-446c-ad45-5f74b5192f56 · outbound

This paper cites Pre-FEC and Post-FEC BER as Criteria for Optimizing Wireline Transceivers,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Pre-FEC and Post-FEC BER as Criteria for Optimizing Wireline Transceivers,

Reference 49

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Observation ac94b208-934c-490b-9967-8b1799a3ef9d · outbound

This paper cites The GAP Benchmark Suite.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation The GAP Benchmark Suite

Reference 50

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Observation 935b875b-14c7-4c05-9897-c550c42042e8 · outbound

This paper cites SPEC Bench- marks and Tools.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation SPEC Bench- marks and Tools

Reference 51

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Observation d0bde326-1019-4de2-be53-dcb2dd46248d · outbound

This paper cites Splash- 4: A Modern Benchmark Suite with Lock-Free Constructs,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Splash- 4: A Modern Benchmark Suite with Lock-Free Constructs,

Reference 52

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Observation 4dfc7efe-7b77-46cc-b1a6-d5aa88b88fa3 · outbound

This paper cites Rodinia: A Benchmark Suite for Heterogeneous Com- puting,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Rodinia: A Benchmark Suite for Heterogeneous Com- puting,

Reference 53

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Observation 0d5cc23a-5b0e-4962-90ac-9de94c100277 · outbound

This paper cites XSBench: The Development and Verification of a Performance Abstraction for Monte Carlo Reactor Analysis,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation XSBench: The Development and Verification of a Performance Abstraction for Monte Carlo Reactor Analysis,

Reference 54

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.476906Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 5bac188c-5235-44a8-af0d-2207371bd218 · outbound

This paper cites Core-to-Core Latency Measurement Tool.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Core-to-Core Latency Measurement Tool

Reference 55

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.481298Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 11cacf41-f583-4f6e-a1ae-bded08a8d446 · outbound

This paper cites Addressing End-to-End Memory Access Latency in NoC-Based Multicores,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Addressing End-to-End Memory Access Latency in NoC-Based Multicores,

Reference 56

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.486385Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 4af1ace4-a3ef-4f51-9d9b-341799f8c5cf · outbound

This paper cites Pitstop: Enabling a Virtual Net- work Free Network-on-Chip,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Pitstop: Enabling a Virtual Net- work Free Network-on-Chip,

Reference 57

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.492009Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 01cc035d-76f7-47f3-b755-ca7d4bed7476 · outbound

This paper cites A Quad-Chiplet AI SoC with Full-Chip Scalable Mesh Over 16Gb/s UCIe-Advanced Die-to-Die Interface for Large-Scale AI Inferencing,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation A Quad-Chiplet AI SoC with Full-Chip Scalable Mesh Over 16Gb/s UCIe-Advanced Die-to-Die Interface for Large-Scale AI Inferencing,

Reference 58

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.496951Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation bda9da6d-3087-45b2-b3aa-14c8ea18d410 · outbound

This paper cites Zeppelin: An SoC for Multichip Architectures,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Zeppelin: An SoC for Multichip Architectures,

Reference 59

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.502047Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation db478be4-a129-4aa4-8995-795b1f0f4b4e · outbound

This paper cites Compute Express Link (CXL) 3.1 Specification.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Compute Express Link (CXL) 3.1 Specification

Reference 60

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.507030Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f2528adf-d53a-48ed-ba56-b2a8f736089a · outbound

This paper cites Scaling Out Chip Interconnect Networks with Implicit Sequence Numbers,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Scaling Out Chip Interconnect Networks with Implicit Sequence Numbers,

Reference 61

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.512123Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 224f03a5-a69a-4ed3-ab3a-cbaab820b68d · outbound

This paper cites Sapphire Rapids: The Next-Generation Intel Xeon Scalable Processor,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Sapphire Rapids: The Next-Generation Intel Xeon Scalable Processor,

Reference 62

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.516803Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 1f9136ad-e57d-4de8-8fbd-5242a6220f88 · outbound

This paper cites Invalidate or Update? Revisiting Coherence for Tomorrow’s Cache Hierarchies,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Invalidate or Update? Revisiting Coherence for Tomorrow’s Cache Hierarchies,

Reference 63

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.521493Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 332f41d5-f701-473d-b087-f9d386c9247b · outbound

This paper cites An Adaptive Cache Coherence Pro- tocol Optimized for Producer-Consumer Sharing,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation An Adaptive Cache Coherence Pro- tocol Optimized for Producer-Consumer Sharing,

Reference 64

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.526664Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 9662c68a-eca3-4b99-a164-9c731387ca22 · outbound

This paper cites Anatomy of the gem5 Simulator.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Anatomy of the gem5 Simulator

Reference 65

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.531934Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 6aa322bd-2683-4eb5-a082-0f748ccc678b · outbound

This paper cites Demystify- ing Complex Workload-DRAM Interactions: An Experimental Study,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Demystify- ing Complex Workload-DRAM Interactions: An Experimental Study,

Reference 66

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.537362Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 58b7baa0-24ed-45d4-9d65-efe047a35f88 · outbound

This paper cites A First-Order Superscalar Processor Model,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation A First-Order Superscalar Processor Model,

Reference 67

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.541967Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 3f05085c-cba5-428b-9d32-624608490cd3 · outbound

This paper cites A Mechanistic Performance Model for Superscalar Out-of-Order Processors,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation A Mechanistic Performance Model for Superscalar Out-of-Order Processors,

Reference 68

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.547390Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation d0388e71-72b7-4e5b-b72c-2a0b5ce783d7 · outbound

This paper cites Callback: Efficient Synchronization without Invalidation with a Directory Just for Spin-Waiting,.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation Callback: Efficient Synchronization without Invalidation with a Directory Just for Spin-Waiting,

Reference 69

Resolution: unresolved; no resolver link, observed 2026-07-31T20:44:51.551686Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Coverage vector

Reference resolution

Outbound references

Pith citing papers