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The gem5 Simulator: Version 20.0+
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The open-source and community-supported gem5 simulator is one of the most popular tools for computer architecture research. This simulation infrastructure allows researchers to model modern computer hardware at the cycle level, and it has enough fidelity to boot unmodified Linux-based operating systems and run full applications for multiple architectures including x86, Arm, and RISC-V. The gem5 simulator has been under active development over the last nine years since the original gem5 release. In this time, there have been over 7500 commits to the codebase from over 250 unique contributors which have improved the simulator by adding new features, fixing bugs, and increasing the code quality. In this paper, we give and overview of gem5's usage and features, describe the current state of the gem5 simulator, and enumerate the major changes since the initial release of gem5. We also discuss how the gem5 simulator has transitioned to a formal governance model to enable continued improvement and community support for the next 20 years of computer architecture research.
Forward citations
Cited by 10 Pith papers
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DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation
Runtime end-to-end inter-chiplet PHY modeling in gem5 changes packet-latency composition and shifts IPC by 6.8% on average (up to 27.6%) versus fixed-latency HeteroGarnet links.
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Automated Synthesis of Heterogeneous, Hierarchical, Scoped Coherence Protocols
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Microflow: Microarchitectural Causal Observability for Deep Cross-Layer Analysis and Optimization
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ML for the hKLM at the 2nd Detector
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Pickle: Precise, Flexible Cross-Core Last-level Cache Data Prefetching for Irregular Memory Accesses
Pickle is a software-defined, hardware-managed LLC prefetcher whose simulated BFS speedups (1.32x geomean) are real but narrower than the abstract's GAP/NAS claims.
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Advancing Cloud Computing Capabilities on gem5 by Implementing the RISC-V Hypervisor Extension
The paper reports a working implementation of the RISC-V H hypervisor extension in gem5, validated by booting Xvisor with guest Linux and by running nine MiBench workloads with and without a VM.
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ShieldMMU: Detecting and Defending against Controlled-Channel Attacks in Shielding Memory System
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Anatomy of the gem5 Simulator: AtomicSimpleCPU, TimingSimpleCPU, O3CPU, and Their Interaction with the Ruby Memory System
In gem5, the Ruby memory subsystem dominates simulation time for the AtomicSimpleCPU and TimingSimpleCPU, chiefly during instruction fetch, while the O3CPU spends most of its time building instruction objects and runn...
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