Paper Citation Record · LEDGER

Toward Automated Potential Primary Asset Identification in Verilog Designs

As of 9 August 2026, this Paper Citation Record lists 15 of 15 outbound references and 1 inbound Pith citation observation for arXiv:2502.04648.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2502.04648 v1

Coverage vector

measured 15 of 15 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-08T22:02:17.507105Z

measured 16 of 16 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-08T06:32:00.761636+00:00

measured 1 of 1 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-06T22:55:09.218698Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: pith, observed 2026-08-06T22:55:09.606281Z

Reference resolution

15 of 15 outbound references displayed

verified exact2
verified fuzzy12
unresolved1
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 01b065cc-0a12-4b72-8a64-cabd25a85131 · outbound

This paper cites Hsdl: A security development lifecycle for hardware technologies,.

Toward Automated Potential Primary Asset Identification in Verilog Designs Hsdl: A security development lifecycle for hardware technologies,

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-08T22:02:38.343479Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation fbe43e65-f870-4de4-897b-44cb798133d8 · outbound

This paper cites Don’t CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design,.

Toward Automated Potential Primary Asset Identification in Verilog Designs Don’t CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design,

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-08T22:02:38.334175Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation ac2b63a4-4fe0-441f-a852-700256b0219d · outbound

This paper cites Mishra, S.

Toward Automated Potential Primary Asset Identification in Verilog Designs Mishra, S

Reference 3

Resolution: verified exact; doi, observed 2026-08-08T22:02:17.536281Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation 95c58775-7dfc-4da1-972b-d15f220ffc3a · outbound

This paper cites Asset Identification for Electronic Design IP,.

Toward Automated Potential Primary Asset Identification in Verilog Designs Asset Identification for Electronic Design IP,

Reference 4

Resolution: unresolved; no resolver link, observed 2026-08-08T22:02:17.471859Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 4544337d-e912-44c1-9729-46908dec94b0 · outbound

This paper cites Automatic Asset Identification for Assertion-Based SoC Security Ver- ification,.

Toward Automated Potential Primary Asset Identification in Verilog Designs Automatic Asset Identification for Assertion-Based SoC Security Ver- ification,

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-08T22:02:38.324535Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation 4117ab19-72c0-4698-ac1f-66dc0ff98249 · outbound

This paper cites accellera.org,.

Toward Automated Potential Primary Asset Identification in Verilog Designs accellera.org,

Reference 6

Resolution: verified fuzzy; raw_fallback, observed 2026-08-08T22:02:38.315285Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation f33a634b-45b8-42a0-8c93-c1a7d7cf5fde · outbound

This paper cites SAIF: Automated Asset Identification for Security Verification at the Register Transfer Level,.

Toward Automated Potential Primary Asset Identification in Verilog Designs SAIF: Automated Asset Identification for Security Verification at the Register Transfer Level,

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-08T22:02:38.305793Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation 8fd8dbe6-3d2b-4940-bdba-b6306fe2c31c · outbound

This paper cites Arm security technology: Building a secure system using trust- zone technology,.

Toward Automated Potential Primary Asset Identification in Verilog Designs Arm security technology: Building a secure system using trust- zone technology,

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-08T22:02:38.296193Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation ba8175d1-b068-4d67-8966-7e82d064a31d · outbound

This paper cites What is the CIA Triad and Why is it important?.

Toward Automated Potential Primary Asset Identification in Verilog Designs What is the CIA Triad and Why is it important?

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-08T22:02:38.286618Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation 5563070d-66ff-4f00-be89-157fcc12ffb0 · outbound

This paper cites CWE - Common Weakness Enumeration — cwe.mitre.org,.

Toward Automated Potential Primary Asset Identification in Verilog Designs CWE - Common Weakness Enumeration — cwe.mitre.org,

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-08T22:02:38.276507Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation 1ca81948-a31e-47e5-a06d-8b9a083f0081 · outbound

This paper cites Special Ses- sion: CAD for Hardware Security - Promising Directions for Automation of Security Assurance,.

Toward Automated Potential Primary Asset Identification in Verilog Designs Special Ses- sion: CAD for Hardware Security - Promising Directions for Automation of Security Assurance,

Reference 11

Resolution: verified fuzzy; raw_fallback, observed 2026-08-08T22:02:38.265189Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation 1ed214c8-418c-469c-b7f7-885bfd5872ef · outbound

This paper cites System-on-Chip Platform Security Assurance: Architecture and Validation,.

Toward Automated Potential Primary Asset Identification in Verilog Designs System-on-Chip Platform Security Assurance: Architecture and Validation,

Reference 12

Resolution: verified exact; raw_fallback, observed 2026-08-08T22:02:27.882998Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation 54b53454-fc91-481c-8c7f-c01cc5be2a64 · outbound

This paper cites Introduction to hardware- oriented security for MPSoCs,.

Toward Automated Potential Primary Asset Identification in Verilog Designs Introduction to hardware- oriented security for MPSoCs,

Reference 13

Resolution: verified fuzzy; raw_fallback, observed 2026-08-08T22:02:38.255549Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation 7cbc98bf-59fd-452e-9373-5f1350c365e0 · outbound

This paper cites Security Verification of the OpenTitan Hardware Root of Trust,.

Toward Automated Potential Primary Asset Identification in Verilog Designs Security Verification of the OpenTitan Hardware Root of Trust,

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-08-08T22:02:38.245511Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation 7811bf61-1bc4-4beb-a294-4ea1778c39da · outbound

This paper cites Open source silicon root of trust (RoT) | OpenTitan.

Toward Automated Potential Primary Asset Identification in Verilog Designs Open source silicon root of trust (RoT) | OpenTitan

Reference 15

Resolution: verified fuzzy; raw_fallback, observed 2026-08-08T22:02:38.235547Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Pith citing papers

Observation 122dfc22-8d3e-4e4d-9f4d-adcd816770db · inbound

SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models cites this paper.

SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models Toward Automated Potential Primary Asset Identification in Verilog Designs

Reference 43

Resolution: verified exact; local_arxiv, observed 2026-08-06T22:55:09.611190Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.