Paper Citation Record · LEDGER

CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

As of 8 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 14 inbound Pith citation observations for arXiv:2409.12993.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2409.12993 v2

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 14 of 14 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-08T06:32:00.761636+00:00

measured 14 of 14 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-07T10:45:07.073518Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-07-04T12:39:49.548439Z

Reference resolution

0 of 0 outbound references displayed

verified exact0
verified fuzzy0
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation 1fc6efa9-c991-4468-8e0a-5fb11c1f3688 · inbound

hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation cites this paper.

hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

Reference 21

Resolution: unresolved; no resolver link, observed 2026-08-07T10:45:07.073518Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 33e4f370-1d2e-4f73-9dcf-08f4524825a5 · inbound

QiMeng: Fully Automated Hardware and Software Design for Processor Chip cites this paper.

QiMeng: Fully Automated Hardware and Software Design for Processor Chip CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

Reference 43

Resolution: unresolved; no resolver link, observed 2026-08-07T10:34:04.408164Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ae946843-c748-4368-8668-7a43df3ceda5 · inbound

ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation cites this paper.

ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

Reference 20

Resolution: unresolved; no resolver link, observed 2026-08-07T10:18:59.351726Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation d9376281-9a54-4627-acda-4289cfff38d4 · inbound

Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems cites this paper.

Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-07T00:31:00.486398Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 4610b089-b8fe-4eb5-854b-ea3993bbdfb6 · inbound

DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs cites this paper.

DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

Reference 22

Resolution: unresolved; no resolver link, observed 2026-08-06T20:40:17.834521Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 05fd4c34-5c1c-42b9-9967-53ac7437e132 · inbound

ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning cites this paper.

ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

Reference 16

Resolution: verified exact; arxiv_id, observed 2026-05-19T06:52:08.321202Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation b84b810b-0b11-4318-a365-c6fdd17a71a5 · inbound

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation cites this paper.

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

Reference 23

Resolution: unresolved; no resolver link, observed 2026-08-06T18:54:04.068314Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation fbc4af32-f4e2-4353-91f4-2aab8d6f620a · inbound

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs cites this paper.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:52.696047Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f81278ce-87d3-4e72-8deb-4cc18a8bb516 · inbound

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning cites this paper.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

Reference 19

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:23.394069Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a6affd56-9c68-43d1-880f-f2ab95791147 · inbound

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog cites this paper.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

Reference 12

Resolution: verified exact; arxiv_id, observed 2026-05-11T21:31:14.713384Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation db636adc-fab3-4a6b-95a7-7ccd531b096c · inbound

CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs cites this paper.

CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

Reference 4

Resolution: verified exact; arxiv_id, observed 2026-07-02T15:57:07.376172Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation a280b3e7-f921-46b9-a9c0-aea7416e25cf · inbound

VeriPilot: An LLM-Powered Verilog Debugging Framework cites this paper.

VeriPilot: An LLM-Powered Verilog Debugging Framework CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

Reference 4

Resolution: verified exact; arxiv_id, observed 2026-07-04T12:39:49.550229Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation 87a06668-fc18-4806-8031-4db927c82bb4 · inbound

Agentic Hardware Design as Repository-Level Code Evolution cites this paper.

Agentic Hardware Design as Repository-Level Code Evolution CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

Reference 13

Resolution: verified exact; arxiv_id, observed 2026-07-01T18:45:58.303456Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.

Observation f7bda274-0105-40af-9963-f906113e0188 · inbound

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs cites this paper.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

Reference 19

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:10.263615Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.