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RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

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arxiv 2308.05345 v3 pith:Z6XASJT3 submitted 2023-08-10 cs.LG cs.AR

classification cs.LGcs.AR
keywords designbenchmarkgoallanguagenamedgeneratinginstructionslarge
verification ladder T0 review T1 audit T2 compute T3 formal
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Inspired by the recent success of large language models (LLMs) like ChatGPT, researchers start to explore the adoption of LLMs for agile hardware design, such as generating design RTL based on natural-language instructions. However, in existing works, their target designs are all relatively simple and in a small scale, and proposed by the authors themselves, making a fair comparison among different LLM solutions challenging. In addition, many prior works only focus on the design correctness, without evaluating the design qualities of generated design RTL. In this work, we propose an open-source benchmark named RTLLM, for generating design RTL with natural language instructions. To systematically evaluate the auto-generated design RTL, we summarized three progressive goals, named syntax goal, functionality goal, and design quality goal. This benchmark can automatically provide a quantitative evaluation of any given LLM-based solution. Furthermore, we propose an easy-to-use yet surprisingly effective prompt engineering technique named self-planning, which proves to significantly boost the performance of GPT-3.5 in our proposed benchmark.

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Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems

    cs.AR 2025-06 conditional novelty 6.0 of 10

    On three NIST crypto standards (AES, DSS, HMAC), Spec2RTL-Agent generates RTL via a multi-agent pipeline from pseudocode to Python to synthesizable C++, reporting 3/3 correct designs with about 4.3 human interventions...

  2. ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols

    cs.AR 2025-06 conditional novelty 6.0 of 10

    A new benchmark, ProtocolLLM, evaluates LLM-generated SystemVerilog for SPI, I2C, UART, and AXI and finds most models fail timing-accurate functional checks.

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