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REVIEW 3 major objections 4 minor 33 references

An LLM agent can schedule chip design optimization as well as human engineers, with far less manual effort.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

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2026-08-02 18:12 UTC pith:ZT7E7IZQ

load-bearing objection A genuinely new LLM-agent framework for long-horizon ECO scheduling, with sensible ablations and a real tool evaluation — but the headline margins come from unseeded single runs and a hidden knowledge store, so referee with a request for variance and artifacts. the 3 major comments →

arxiv 2603.13767 v2 pith:ZT7E7IZQ submitted 2026-03-14 cs.AR

Retrieve, Schedule, Reflect: LLM Agents for Chip QoR Optimization

Yikang Ouyang , Yang Luo , Dongsheng Zuo , Yuzhe Ma This is my paper
classification cs.AR
keywords LLM agentschip designQoR optimizationschedulingretrieval-augmented generationPareto reflectionECOtiming closure
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper tries to establish that the long-horizon scheduling of chip Quality-of-Results (QoR) optimization—deciding which objective (timing, power, area) to attack next and which EDA-tool algorithm to run—can be automated by an LLM agent. The agent is grounded in a search-tree library of expert-written scheduling templates, retrieved by similarity to the current design state, and it improves across rounds by reflecting on Pareto-optimal traces. On 8 benchmark chip designs, the paper reports that this approach leaves only 0.23% of original total negative slack unsolved, outperforming a reinforcement-learning baseline (which leaves 10.92%) and matching human engineers. The paper also claims a more than 4× speedup over RL and the ability to follow natural-language trade-off instructions, such as trading 5% worst-slack for about 20% lower combinational power. If correct, this would reduce the need for continuous expert monitoring of optimization runs and make customizable QoR objectives practical.

Core claim

The paper's central claim is that chip QoR optimization can be treated as an LLM-driven scheduling problem, not a single-shot parameter search. It introduces a Retrieve–Schedule–Reflect loop: a scheduler queries a database of natural-language scheduling paths (the search tree), an executor turns the retrieved advice into legal EDA tool commands, and a reflector distills Pareto-optimal historical traces into scheduling and execution guidance for the next round. The authors report that on 8 ASAP7 open-source designs, this framework achieves post-optimization total slack leaving only 0.23% of the original negative slack unsolved (versus 10.92% for a reinforcement-learning baseline and 0.51% for

What carries the argument

The central object is the scheduling search tree (ST): a set of nodes, each containing an objective (timing/power/area), a natural-language design-state description, a strategy snippet, and tool-manual references. Paths through the ST are extracted into a database D; at runtime the scheduler embeds the current design state and QoR history, retrieves the top-k most cosine-similar paths, and uses them as step-by-step scheduling templates. The second load-bearing mechanism is Pareto-driven reflection: terminal QoR vectors from completed rounds are filtered to the Pareto front, and a reflector agent writes two short natural-language summaries—one about objective ordering (scheduling reflection)

Load-bearing premise

The search tree—the paper's claimed source of 'natural-language expertise'—is asserted to be built from academic papers and engineer input, but its contents are not released or demonstrated; if the tree is thin, ad hoc, or tuned to the benchmark, the RAG advantage evaporates.

What would settle it

Inspect the released search tree and count the number of distinct paths per objective and design-state type; then run the framework on a new set of designs from a different PDK or with a randomly perturbed tree, and check whether the claimed total-slack improvement and the RAG-ablation gap (from -8.44e2 to -1.56e3 in Table 3) still appear. If the gap shrinks to noise or the framework fails on unfamiliar designs, the central claim that expert-grounded RAG is essential would be falsified.

Watch this falsifier. Get emailed when new claim-graph text bears on it.

If this is right

  • If the framework genuinely matches human-engineer QoR, design teams could reduce manual ECO scheduling effort, reserving engineers for final review rather than iterating optimization runs.
  • The reported 4× speedup over RL suggests that knowledge-grounded search can cut the exploration cost of black-box optimization, a pattern that could transfer to other engineering domains with iterative tool usage.
  • Natural-language trade-off instructions become a practical way to steer multi-objective optimization, e.g., explicitly trading timing margin for power, without redefining a reward function.
  • The Pareto-reflection mechanism provides a general recipe: any iterative optimizer that can summarize its own history in text can improve across restarts, which extends beyond chips to other design flows.
  • The open-sourced code and data would let others test whether the framework's advantage depends on the specific search tree and models, or whether it persists across new designs and process nodes.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • A testable extension is to blind-audit the search tree: if the same tree is applied to designs outside the ICCAD'24 ASAP7 benchmark (different process nodes, macros, or clock frequencies), the RAG ablation gap should persist; if it collapses, the tree is likely overfit to the benchmark.
  • The ablation table suggests that reflection contributes more than RAG on timing (removing reflection degrades total slack from -8.44e2 to -1.83e3, while removing RAG degrades to -1.56e3). An editor might infer that the framework's robustness depends more on cross-round feedback than on the specific knowledge base, which has implications for how easily it can be ported.
  • The paper reports LLM token costs of $1.25 for a full run on GPT-5-mini; if LLM inference costs continue to fall, the economic barrier to using such agents in production EDA flows would shrink enough to make the approach practical for routine design closure.
  • A natural follow-up study would stress-test the language-instruction capability by asking the agent to follow conflicting or unusual trade-offs (e.g., 'minimize leakage only' or 'fix only hold time'), checking whether it still respects hard constraints.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. The paper proposes an agentic LLM framework, Retrieve-Schedule-Reflect, for automating the long-horizon scheduling of iterative chip QoR optimization in commercial EDA tools. Three agents (scheduler, executor, reflector) operate in rounds: the scheduler retrieves natural-language scheduling templates from a search tree via RAG, the executor translates advice into legal EDA commands using tool-manual retrieval, and the reflector summarizes Pareto-optimal traces into scheduling and execution feedback. Experiments on 8 ASAP7 designs from the ICCAD'24 dataset report that the framework outperforms an A3C RL baseline in timing improvement (average total slack ratio 0.23% vs 10.92%), achieves better or comparable power/area, runs in about 3.5h vs 15.4h, and is comparable to a human engineer. Ablations show that removing RAG or reflection degrades timing, and the framework can follow natural-language preferences such as allowing 5% worst-slack degradation to reduce combinational power.

Significance. If the empirical claims are robust, the work would be a useful step toward automating a labor-intensive part of chip design: the schedule-execute-reflect loop currently requiring expert engineers. The design is attractive: human-interpretable search-tree templates, RAG for knowledge grounding, Pareto-driven reflection, and the ability to express custom objectives in natural language are all credible and practical contributions. The authors commit to releasing code and design data, which would strengthen reproducibility. However, the current evidence is not yet sufficient to establish the central quantitative claims: all headline comparisons rest on single runs of a temperature=1 LLM pipeline with no seed control, and the knowledge store that drives the RAG advantage is not released or fully specified. The result is promising but needs additional statistical validation and transparency before the claims can be accepted.

major comments (3)
  1. [§5.1, §B.1, Tables 1–3] All reported QoR numbers are single-run point estimates from a stochastic pipeline: temperature=1, top_p=1 for every LLM call (B.1), no seed is reported, and the RL baseline itself is stochastic. The central claim of “10% better timing” and the RAG ablation effect (Table 3: Ours total slack -8.44e2 vs w/o-RAG -1.56e3) could be within run-to-run variation. I request repeated runs with multiple seeds (at least 3–5) for the full system, the RAG/reflection ablations, and the RL baseline, with means and standard deviations or confidence intervals. Without this, Contribution 4 is not statistically established.
  2. [§3.1, Appendix A] The search tree (ST) is the central source of “expertise grounding,” but its construction is asserted rather than demonstrated: the paper states it is “built from academic papers and reports” and “filtered by engineers” (Appendix A), yet only one example path is shown, and the full tree, filtering protocol, and coverage criteria are not released. Since the w/o-RAG ablation roughly doubles the remaining total slack (Table 3), the claimed advantage depends critically on the quality and transferability of this ST. I ask the authors to release the ST (or a substantial excerpt) and to provide concrete coverage criteria, construction details, and some evidence that the ST is not tuned to the specific 8 benchmark designs (e.g., evaluation on a held-out design or a different PDK).
  3. [§5.1, Table 1 (Human baseline)] The human baseline is described only as “asking an experienced engineer to manually schedule the optimization process for 10 rounds.” No information is given about the engineer’s experience, instructions, or inter-person variability. The human row shows exactly zero total slack on five of eight designs, which is surprising and suggests that different stopping criteria or effort levels may have been used. The comparison “comparable to human engineers” is therefore not yet well supported. Please specify the protocol, the engineer’s background, the exact objective/budget given, and ideally report results from more than one engineer or repeated sessions.
minor comments (4)
  1. [§2.4 and elsewhere] Typo: “an multi-agent framework” should be “a multi-agent framework.” Also “scheudling” in the introduction should be “scheduling.”
  2. [References] The reference list contains duplicate entries for Mnih et al. (2016a and 2016b), which are the same paper; the in-text citation in B.3 uses 2016b. Also, §5.4 cites DeepSeek-V3.2 as (Liu et al., 2025b), but the reference list associates DeepSeek-V3.2 with Liu et al. (2025a); the 2025b entry is for MM-Agent. Please correct these.
  3. [§5.5, Figure 5] The runtime breakdown pie charts are hard to read in the current rendering; consider replacing them with a stacked bar chart or a table with percentages.
  4. [§5.1] The statement that code segments restricted by the tool license are replaced with “mock equivalents” is helpful, but it would be useful to state explicitly which parts are mocked and how a reader can substitute real commands; otherwise the reproducibility promise is hard to evaluate.

Circularity Check

0 steps flagged

No significant circularity: the core empirical claims are anchored by external EDA reports (PrimeECO) and independent benchmark designs, with no fitted parameter renamed as a prediction.

full rationale

The paper's contribution is an evaluated agent workflow, not a derivation whose output is forced by its inputs. The QoR numbers in Tables 1-3 are measured by an external golden tool: 'All optimizations and report generation are performed using Synopsys PrimeECO, a widely used golden tool for QoR analysis and ECO optimization.' The search tree used for RAG is constructed externally from 'academic papers and reports with engineer input so that the encoded schedules reflect realistic optimization practice rather than arbitrary sequences' (Sec. 3.1, Appendix A), and the paper does not report fitting any ST node or retrieval parameter to the target QoR values of the eight ICCAD'24 ASAP7 designs. Equations (1)-(12) define representations (node, path, cosine similarity, top-k, trace, Pareto set) and do not contain a parameter fitted to the reported outcomes; the Pareto filter is a selection rule, not a predictor. The only overlapping-author citation is Bai et al. 2024 for the A3C RL baseline: 'We develop and A3C RL algorithm (Mnih et al., 2016b) that is used in EDA tasks (Bai et al., 2024) as baseline.' This is an implementation reference for a comparison method, with hyperparameters given in B.3, and the resulting outputs are externally measured; it is not load-bearing for the paper's central claim. Legitimate concerns remain — the full ST content is not released, all LLM runs use temperature=1/top_p=1 with no seeds (B.1), and single-run point estimates are reported — but these are reproducibility/statistical-validity risks, not circularity under the quoted reduction test.

Axiom & Free-Parameter Ledger

6 free parameters · 5 axioms · 1 invented entities

The framework contributes no new physical entities; its 'derivation' is an empirical comparison. The free parameters are hand-set hyperparameters that shape the headline numbers: the 10-round restart budget, ≤10 iterations per round, RAG top-k (never stated), temperature=1/top_p=1, hand-written prompts, and the author-chosen RL reward weights that define the baseline. The axioms are dominated by one unverifiable premise — the search tree is expert-quality and transferable but is not released. Remaining axioms are standard EDA/LLM domain assumptions.

free parameters (6)
  • Number of rounds (R_max) = 10
    Hand-set budget of restarts from the unoptimized design; the final round's QoR is reported, so this budget directly shapes the headline result.
  • Iterations per round (I_max) = 10
    Hand-set cap on schedule–execute iterations per round; identical to the human baseline budget (§5.1).
  • RAG top-k = not reported
    The retrieval threshold in Eq. (4) is never stated; it controls how much expert guidance the scheduler and executor see.
  • LLM sampling temperature / top-p = 1.0 / 1.0
    Set in B.1 to maximize stochasticity; unseeded sampling means the reported numbers are a single draw from a random process.
  • RL baseline reward weights and hyperparameters = TS=10, WS=3, power=3, area=3; violation bonus=10; gamma=0.99, lr=1e-3
    Author-chosen for the A3C baseline (B.3); tuning fairness versus the proposed method is not analyzed.
  • Hand-written prompt templates = as in Appendix D
    Scheduler/executor/reflector prompts encode the task framing and response formats; alternative phrasings would change outputs.
axioms (5)
  • ad hoc to paper The search tree encodes valid, transferable expert scheduling knowledge.
    §3.1 and Appendix A describe construction from papers and engineer filtering, but the ST content is not released; the method's expertise grounding is asserted, not independently verifiable.
  • domain assumption Slack (WNS/TNS) is an adequate primary measure of timing quality, and negative slack means functional failure.
    §5.1–5.2; standard EDA practice, but it determines how all methods and custom trade-offs are scored.
  • domain assumption GPT-5-mini reliably interprets EDA reports and generates legal EDA commands when grounded by retrieved manual snippets.
    §4.1 and §5.1; no command-success rate or parsing-error statistics are reported, and the manual is license-restricted/mocked.
  • standard math Pareto dominance over (timing, power, area) terminal vectors is the correct optimality criterion for trace selection.
    §4.2.1, Eqs. 10–12; standard definition, though with three objectives the Pareto front can be large and the selection's sensitivity is untested.
  • domain assumption The ICCAD'24 ASAP7 benchmark designs are representative of practical ECO workloads.
    §5.1; all eight designs come from one benchmark family with severely negative pre-optimization slack (Table 5), so generalization to healthier designs is untested.
invented entities (1)
  • Search-tree path database D of natural-language scheduling templates no independent evidence
    purpose: Knowledge store the scheduler and executor retrieve from (Eqs. 3–8); encodes expert objective ordering and tool-use strategy.
    The ST is human-authored for this paper, only one example path is shown (Appendix A), and its full content is not released, so its quality and coverage cannot be independently checked.

pith-pipeline@v1.3.0-alltime-deepseek · 19146 in / 22965 out tokens · 219524 ms · 2026-08-02T18:12:54.325992+00:00 · methodology

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read the original abstract

Modern chip design requires multi-objective optimization of timing, power, and area under stringent time-to-market constraints. Although powerful optimization algorithms are integrated into EDA tools, achieving high QoR hinges on effective long-horizon scheduling, which relies heavily on manual expert intervention. To address this issue and automate chip design, we propose an agentic LLM framework that schedules chip optimizations through direct interaction with EDA tools. The agent is grounded in natural language expertise expressed as a search tree through retrieval-augmented generation (RAG). We further improve scheduling quality with Pareto-driven QoR feedback through language reflection. Experimental results show that, compared with black-box search methods such as reinforcement learning, our framework achieves 10% greater timing improvement while consuming less power and area, with more than 4x speedup. The post-optimization QoR is also comparable to that achieved by human experts. Finally, the agent supports customized tasks expressed in natural language, enabling preferential QoR trade-offs. The code and chip design data will be publicly available at https://github.com/YiKangOY/Open-LLM-ECO.

Figures

Figures reproduced from arXiv: 2603.13767 by Dongsheng Zuo, Yang Luo, Yikang Ouyang, Yuzhe Ma.

Figure 1
Figure 1. Figure 1: Chip QoR optimization as an iterative schedule–execute– reflect workflow. 2025; Lu et al., 2021; 2023b). While these algorithms are integrated into EDA tools and can be invoked easily, achieving competitive QoR still re￾quires extensive human effort. Due to the NP-hard nature of chip optimization (Ning, 1994), QoR improvement often saturates and may be trapped in local minima after several iterations (Neto… view at source ↗
Figure 2
Figure 2. Figure 2: Scheduling strategy constructed as a search tree and path-based RAG. ples (Lewis et al., 2020). Second, reflection reviews sum￾maries of failures/successes and uses them to refine future schedules, improving qualities in iterative workflows (Shinn et al., 2023). 2.4. Problem Formulation In this paper, we aim to automate the scheduling of chip QoR optimization with an multi-agent framework. Given a designer… view at source ↗
Figure 3
Figure 3. Figure 3: Overview of our framework. (a) Rounds of chip optimization scheduling. (b) Iterative retrieve-schedule-reflect with execution with in one round. (c) Example prompt and agent response snippets. 4. Agentic Schedule–Execute–Reflect Framework Building upon the ST-based RAG in Section 3, we present an agentic framework for long-horizon chip QoR optimiza￾tion scheduling. An overview is shown in [PITH_FULL_IMAGE… view at source ↗
Figure 4
Figure 4. Figure 4: QoR trend within the last scheduled optimization round of “mempool tile wrap” design. worst slack and total slack, where worst slack captures the most critical timing path and total slack reflects the over￾all severity of timing violations. For power and area, lower values indicate better QoR. All optimizations and report gen￾eration are performed using Synopsys PrimeECO, a widely used golden tool for QoR … view at source ↗
Figure 5
Figure 5. Figure 5: Runtime breakdown for NVDLA partition m and hid￾den1. Each pie chart shows the percentage of total runtime spent in LLM interaction and EDA tool. The Other section denotes other runtime costs like loading chip designs into EDA tools. We further provide a runtime breakdown on a large design (NVDLA partition m) and a small design (hidden1) in terms of area in [PITH_FULL_IMAGE:figures/full_fig_p008_5.png] view at source ↗

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    Pith/arXiv arXiv 2023