Recognition: unknown
Light emitting device for display and display apparatus having the same
Pith reviewed 2026-05-06 21:20 UTC · model grok-4.3
The pith
A light emitting module for displays stacks three semiconductor devices on a circuit board with planarization layers that touch lower connectors to support electrode connections.
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
Core claim
The invention is a light emitting module comprising a circuit board, first second and third semiconductor stacks each containing a first conductivity type layer, a second conductivity type layer and an active layer between them, at least one lower connector, a first bonding layer between the third stack and the board, a second bonding layer between the second stack and the board, a first electrode pad connected to the first stack, a second electrode pad connected to the second stack, a first planarization layer between the first electrode pad and the first stack, and a second planarization layer between the second stack and the second electrode pad, wherein the top surface of the firstplanar
What carries the argument
The contact geometry in which the top surface of the first planarization layer touches the bottom surface of the lower connector, providing both mechanical support and a defined path for electrical integration across the stacked emitters.
If this is right
- Multiple semiconductor stacks can share lower connectors while retaining separate electrode pads for independent control of each emitter.
- Planarization layers create flat surfaces that allow subsequent bonding and electrode formation without topography-induced failures.
- The three-stack vertical arrangement supports multi-color pixels in a footprint smaller than side-by-side emitters.
- Bonding layers simultaneously provide mechanical attachment and electrical isolation or conduction between the stacks and the circuit board.
Where Pith is reading between the lines
- The contact specification may reduce parasitic capacitance or improve heat spreading in high-density micro-LED arrays.
- Yield in mass production would depend on achieving sub-micron alignment accuracy at the planarization-connector interface.
- The same geometry could be adapted to other stacked optoelectronic devices such as sensors or photovoltaic cells that require vertical integration.
- Reliability testing under thermal cycling would reveal whether the planarization contact remains stable over the lifetime of a display product.
Load-bearing premise
The described layer ordering and contact geometry can be fabricated without introducing defects that would prevent reliable electrical operation or optical performance in a finished display product.
What would settle it
Build a device matching the claimed layer sequence and measure whether the first planarization layer top surface physically contacts the lower connector bottom surface while the module still produces light and maintains electrical continuity without shorts or delamination.
Figures
read the original abstract
1 . A light emitting module, comprising: a circuit board; a first semiconductor stack, a second semiconductor stack, and a third semiconductor stack disposed between the first semiconductor stack and the second semiconductor stack, each of the first, second, and third semiconductor stacks including a first conductivity type semiconductor layer and a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; at least one lower connector; a first bonding layer disposed between the third semiconductor stack and the circuit board; a second bonding layer disposed between the second semiconductor stack and the circuit board; a first electrode pad electrically connected to the first semiconductor stack; a second electrode pad electrically connected to the second semiconductor stack; a first planarization layer disposed between the first electrode pad and the first semiconductor stack; and a second planarization layer disposed between the second semiconductor stack and the second electrode pad, wherein a top surface of the first planarization layer is in contact with a bottom surface of the at least one lower connector.
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The manuscript claims a light-emitting module comprising a circuit board, three semiconductor stacks (each with first- and second-conductivity-type layers and an intervening active layer), at least one lower connector, first and second bonding layers, first and second electrode pads, and first and second planarization layers, with the sole geometric constraint that the top surface of the first planarization layer contacts the bottom surface of the lower connector.
Significance. If the recited layer ordering and contact geometry can be realized in a working device, the configuration could in principle simplify vertical integration and planarization for multi-stack LED display modules. However, the complete absence of fabrication sequences, electrical/optical characterization, yield data, or comparison with prior art leaves any practical advantage entirely unverified, rendering the significance speculative at present.
major comments (1)
- Abstract (the sole content provided): the central claim is a physical device structure asserted to be suitable for display use, yet no process details, defect-density estimates, or electrical-contact measurements are supplied to establish that the stated planarization-layer/lower-connector interface can be formed without voids, shorts, or optical scattering that would impair operation. This evidentiary gap is load-bearing for any assertion of a functional module.
minor comments (2)
- The manuscript consists only of a single claim paragraph; standard journal requirements for a methods section, results, figures, and discussion of prior art are entirely missing.
- Notation for the three semiconductor stacks and the two bonding layers is introduced without subsequent reference or differentiation, leaving the reader unable to determine whether the stacks are intended to emit different wavelengths or serve distinct circuit functions.
Simulated Author's Rebuttal
We thank the referee for the careful reading and comments. The submitted document is a U.S. patent application whose purpose is to claim a novel multi-stack semiconductor light-emitting module structure. Patent claims of this type are evaluated on structural novelty, enablement by the full specification, and utility, rather than on experimental characterization data. We address the single major comment below.
read point-by-point responses
-
Referee: Abstract (the sole content provided): the central claim is a physical device structure asserted to be suitable for display use, yet no process details, defect-density estimates, or electrical-contact measurements are supplied to establish that the stated planarization-layer/lower-connector interface can be formed without voids, shorts, or optical scattering that would impair operation. This evidentiary gap is load-bearing for any assertion of a functional module.
Authors: The referee correctly observes that the abstract contains no fabrication sequences or measured data. However, a patent claim is not required to supply such data in the abstract. The independent claim recites a specific, ordered arrangement of three semiconductor stacks, two bonding layers, electrode pads, and planarization layers whose top surface contacts the bottom surface of the lower connector. Enablement under U.S. patent law is judged from the entire specification (detailed description, drawings, and dependent claims), which are part of the filed application but were not reproduced in the excerpt provided to the referee. The recited geometry is intended to be realizable by standard LED and planarization processes already known to practitioners in the field; the inventive contribution lies in the particular layer ordering and contact that simplifies vertical integration. No performance metrics appear because the filing is directed to the structural configuration itself, not to optimized process conditions or yield statistics. revision: no
- The complete patent specification, including the detailed written description and figures that would demonstrate enablement, was not available to the referee.
Circularity Check
Patent claim lists structural elements with no derivation chain
full rationale
The provided document is a US patent abstract that recites a light-emitting module via a list of physical components (circuit board, three semiconductor stacks, bonding layers, electrode pads, planarization layers, lower connector) plus one geometric contact condition. No equations, parameters, predictions, models, or citations appear. Consequently there is no derivation chain, fitted input, self-citation, or ansatz that could reduce to its own inputs. The claim language is self-contained as a structural description; questions of realizability lie outside the abstract itself.
discussion (0)
Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.