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Threshold Accuracy for Quantum Computation

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arxiv quant-ph/9610011 v3 pith:MGUEDPU6 submitted 1996-10-08 quant-ph

classification quant-ph
keywords accuracyerrorquantumassumptionsepsilonerrorsgatepreviously
verification ladder T0 review T1 audit T2 compute T3 formal
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abstract

We have previously (quant-ph/9608012) shown that for quantum memories and quantum communication, a state can be transmitted over arbitrary distances with error $\epsilon$ provided each gate has error at most $c\epsilon$. We discuss a similar concatenation technique which can be used with fault tolerant networks to achieve any desired accuracy when computing with classical initial states, provided a minimum gate accuracy can be achieved. The technique works under realistic assumptions on operational errors. These assumptions are more general than the stochastic error heuristic used in other work. Methods are proposed to account for leakage errors, a problem not previously recognized.

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Forward citations

Cited by 3 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. OpenAlex reports about 110 citations worldwide. Full citation record

  1. Novelty-Based Generation of Continuous Landscapes with Diverse Local Optima Networks

    cs.NE 2026-04 unverdicted novelty 7.0 of 10

    Novelty search generates diverse continuous multimodal landscapes with direct basin definitions, enabling low-cost local optima networks whose features predict evolutionary algorithm performance.

  2. Construction of the full logical Clifford group for high-rate quantum Reed-Muller codes using only transversal and fold-transversal gates

    quant-ph 2026-02 accept novelty 7.0 of 10

    High-rate self-dual quantum Reed–Muller codes admit ancilla-free addressable Clifford gates generated by transversal H and fold-transversal phase gates.

  3. Stabilizer Code-Generic Universal Fault-Tolerant Quantum Computation

    quant-ph 2026-01 unverdicted novelty 6.0 of 10

    Ancilla-mediated protocols enable deterministic universal logical gates on any stabilizer code without ancilla consumption or code modification.

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