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Nick Brown

Identifiers

  • name variant Nick Brown 0.60 · backfill

Papers (69)

  1. Lifting to tensors when compiling scientific computing workloads for AI Engines cs.DC · 2026 · author #1
  2. Is RISC-V ready for High Performance Computing? An evaluation of the Sophon SG2044 cs.DC · 2025 · author #1
  3. Exploring Fast Fourier Transforms on the Tenstorrent Wormhole cs.DC · 2025 · author #1
  4. RISC-V for HPC: An update of where we are and main action points cs.DC · 2025 · author #1
  5. Investigations of multi-socket high core count RISC-V for HPC workloads cs.DC · 2025 · author #1
  6. Seamless acceleration of Fortran intrinsics via AMD AI engines cs.DC · 2025 · author #1
  7. Pragma driven shared memory parallelism in Zig by supporting OpenMP loop directives cs.DC · 2024 · author #4
  8. Accelerating stencils on the Tenstorrent Grayskull RISC-V accelerator cs.DC · 2024 · author #1
  9. Fully integrating the Flang Fortran compiler with standard MLIR cs.DC · 2024 · author #1
  10. Implementing OpenMP for Zig to enable its use in HPC context cs.DC · 2024 · author #2
  11. RISC-V for HPC: Where we are and where we need to go cs.DC · 2024 · author #1
  12. Performance characterisation of the 64-core SG2042 RISC-V CPU for HPC cs.DC · 2024 · author #1
  13. A shared compilation stack for distributed-memory parallelism in stencil DSLs cs.DC · 2024 · author #4
  14. Evaluating Versal AI Engines for option price discovery in market risk analysis cs.DC · 2024 · author #2
  15. Interactive and Urgent HPC: Challenges and Opportunities cs.DC · 2024 · author #2
  16. Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA cs.DC · 2023 · author #2
  17. Fortran performance optimisation and auto-parallelisation by leveraging MLIR-based domain specific abstractions in Flang cs.DC · 2023 · author #1
  18. Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU cs.DC · 2023 · author #1
  19. Fortran High-Level Synthesis: Reducing the barriers to accelerating HPC codes on FPGAs cs.DC · 2023 · author #2
  20. Experiences of running an HPC RISC-V testbed cs.DC · 2023 · author #1
  21. Backporting RISC-V Vector assembly cs.DC · 2023 · author #3
  22. Test-driving RISC-V Vector hardware for HPC cs.DC · 2023 · author #3
  23. Morpheus unleashed: Fast cross-platform SpMV on emerging architectures cs.DC · 2023 · author #4
  24. Task-based preemptive scheduling on FPGAs leveraging partial reconfiguration cs.DC · 2023 · author #2
  25. Web-based volunteer distributed computing for handling time-critical urgent workloads cs.DC · 2022 · author #1
  26. Fast and energy-efficient derivatives risk analysis: Streaming option Greeks on Xilinx and Intel FPGAs cs.DC · 2022 · author #2
  27. Exploring the Versal AI engines for accelerating stencil-based atmospheric advection simulation cs.DC · 2022 · author #1
  28. Performance of the Vipera framework for DSLs on micro-core architectures cs.DC · 2022 · author #2
  29. TensorFlow as a DSL for stencil-based computation on the Cerebras Wafer Scale Engine cs.DC · 2022 · author #1
  30. Programming abstractions for preemptive scheduling in FPGAs using partial reconfiguration cs.AR · 2022 · author #2
  31. Workflows to driving high-performance interactive supercomputing for urgent decision making cs.DC · 2022 · author #1
  32. Low-power option Greeks: Efficiency-driven market risk analysis using FPGAs cs.DC · 2022 · author #2
  33. Predicting batch queue job wait times for informed scheduling of urgent HPC workloads cs.DC · 2022 · author #1
  34. Utilising urgent computing to tackle the spread of mosquito-borne diseases cs.DC · 2021 · author #1
  35. Porting incompressible flow matrix assembly to FPGAs for accelerating HPC engineering simulations cs.DC · 2021 · author #1
  36. Accelerating advection for atmospheric modelling on Xilinx and Intel FPGAs cs.DC · 2021 · author #1
  37. Optimisation of an FPGA Credit Default Swap engine by embracing dataflow techniques cs.DC · 2021 · author #1
  38. Application specific dataflow machine construction for programming FPGAs via Lucent cs.PL · 2021 · author #1
  39. Compact Native Code Generation for Dynamic Languages on Micro-core Architectures cs.PL · 2021 · author #2
  40. Benchmarking micro-core architectures for detecting disasters at the edge cs.DC · 2020 · author #2
  41. Exploring the acceleration of Nekbone on reconfigurable architectures cs.DC · 2020 · author #1
  42. ePython: An implementation of Python for the many-core Epiphany coprocessor cs.DC · 2020 · author #1
  43. Porting the microphysics model CASIM to GPU and KNL Cray machines cs.DC · 2020 · author #1
  44. Extended abstract: Type oriented programming for task based parallelism cs.PL · 2020 · author #1
  45. A comparison of techniques for solving the Poisson equation in CFD cs.DC · 2020 · author #1
  46. In-situ data analytics for highly scalable cloud modelling on Cray machines cs.DC · 2020 · author #1
  47. Leveraging MPI RMA to optimise halo-swapping communications in MONC on Cray machines cs.DC · 2020 · author #1
  48. Driving asynchronous distributed tasks with events cs.DC · 2020 · author #1
  49. A Bespoke Workflow Management System for Data-Driven Urgent HPC cs.DC · 2020 · author #2
  50. iPregel: Vertex-centric programmability vs memory efficiency and performance, why choose? cs.DC · 2020 · author #4
  51. Using machine learning to reduce ensembles of geological models for oil and gas exploration cs.LG · 2020 · author #3
  52. The role of interactive super-computing in using HPC for urgent decision making cs.DC · 2020 · author #1
  53. High level programming abstractions for leveraging hierarchical memories with micro-core architectures cs.DC · 2020 · author #2
  54. It's all about data movement: Optimising FPGA data access to boost performance cs.DC · 2020 · author #1
  55. Exploring the acceleration of the Met Office NERC Cloud model using FPGAs cs.DC · 2020 · author #1
  56. The Technologies Required for Fusing HPC and Real-Time Data to Support Urgent Computing cs.DC · 2020 · author #3
  57. iPregel: Strategies to Deal with an Extreme Form of Irregularity in Vertex-Centric Graph Processing cs.DC · 2020 · author #2
  58. Machine Learning for Gas and Oil Exploration cs.LG · 2020 · author #3
  59. Supercomputing with MPI meets the Common Workflow Language standards: an experience report cs.DC · 2020 · author #2
  60. Weighing up the new kid on the block: Impressions of using Vitis for HPC software development cs.DC · 2020 · author #1
  61. Modelling the earth's geomagnetic environment on Cray machines using PETSc and SLEPc cs.DC · 2020 · author #1
  62. Machine learning on Crays to optimise petrophysical workflows in oil and gas exploration physics.geo-ph · 2020 · author #1
  63. A directive based hybrid Met Office NERC Cloud model cs.DC · 2020 · author #1
  64. A highly scalable Met Office NERC Cloud model cs.SE · 2020 · author #1
  65. A Type-Oriented Graph500 Benchmark cs.PL · 2020 · author #1
  66. A highly scalable approach to solving linear systems using two-stage multisplitting cs.MS · 2020 · author #1
  67. Applying Type Oriented Programming to the PGAS Memory Model cs.PL · 2020 · author #1
  68. Investigating Applications on the A64FX cs.PF · 2020 · author #3
  69. Type oriented parallel programming for Exascale cs.PL · 2016 · author #1

Mentions

  • 2508.13840 #1 · arxiv_oai · confidence 0.70 Nick Brown
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Frequent Coauthors