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Lavanya Subramanian

Identifiers

  • name variant Lavanya Subramanian 0.60 · backfill

Papers (9)

  1. Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems cs.AR · 2018 · author #1
  2. Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost cs.AR · 2018 · author #5
  3. High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems cs.AR · 2018 · author #3
  4. Understanding and Exploiting Design-Induced Latency Variation in Modern DRAM Chips cs.AR · 2016 · author #3
  5. Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism cs.AR · 2016 · author #8
  6. Tiered-Latency DRAM (TL-DRAM) cs.AR · 2016 · author #5
  7. Providing High and Controllable Performance in Multicore Systems Through Shared Resource Management cs.DC · 2015 · author #1
  8. SQUASH: Simple QoS-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators cs.AR · 2015 · author #2
  9. The Blacklisting Memory Scheduler: Balancing Performance, Fairness and Complexity cs.DC · 2015 · author #1

Mentions

  • 1508.03087 #1 · backfill · confidence 0.70 Lavanya Subramanian
  • 1505.07502 #2 · backfill · confidence 0.70 Lavanya Subramanian
  • 1504.00390 #1 · backfill · confidence 0.70 Lavanya Subramanian

Frequent Coauthors