Proposes Distributed Persistence Domain and Persistent CXL Switch to enable low-latency persistence operations at CXL switch level while maintaining crash consistency in disaggregated memory.
IMP: indirect memory prefetcher
2 Pith papers cite this work. Polarity classification is still indexing.
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Pith papers citing it
years
2026 2representative citing papers
TTP is a hardware prefetcher for ray tracing that leverages traversal stack addresses during DFS to prefetch BVH nodes, achieving 1.48x average speedup and 98.92% L1 accuracy in cycle-level simulations.
citing papers explorer
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TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing
TTP is a hardware prefetcher for ray tracing that leverages traversal stack addresses during DFS to prefetch BVH nodes, achieving 1.48x average speedup and 98.92% L1 accuracy in cycle-level simulations.