A hybrid multimodular polynomial reasoning method verifies arithmetic circuits without large-integer arithmetic by running computations in parallel modulo different primes.
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2 Pith papers cite this work. Polarity classification is still indexing.
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Presents a dynamic partitioning parallel SMT framework with core-guided pruning and backbone detection that outperforms sequential Z3 and prior parallel solvers on SMT-COMP 2025 benchmarks across six logics.
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Avoiding Big Integers: Parallel Multimodular Algebraic Verification of Arithmetic Circuits
A hybrid multimodular polynomial reasoning method verifies arithmetic circuits without large-integer arithmetic by running computations in parallel modulo different primes.