First realization of the ν=1/3 fermionic Laughlin state on a 16-qubit IonQ trapped-ion processor via Hamiltonian variational ansatz and symmetry-verification error mitigation, matching exact diagonalization.
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HAL heuristic produces explicit layouts for bivariate bicycle, tile, radial, and Tanner qLDPC codes on multilayer superconducting hardware, demonstrating that open-boundary designs reduce hardware demands with only moderate loss in logical efficiency.
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Realization of fermionic Laughlin state on a quantum processor
First realization of the ν=1/3 fermionic Laughlin state on a 16-qubit IonQ trapped-ion processor via Hamiltonian variational ansatz and symmetry-verification error mitigation, matching exact diagonalization.
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Placing and routing quantum LDPC codes in multilayer superconducting hardware
HAL heuristic produces explicit layouts for bivariate bicycle, tile, radial, and Tanner qLDPC codes on multilayer superconducting hardware, demonstrating that open-boundary designs reduce hardware demands with only moderate loss in logical efficiency.