OpenRTLSet supplies 131k+ Verilog samples with AI-generated descriptions to enable fine-tuning of LLMs for hardware module design.
Chisel: constructing hardware in a scala embedded language,
2 Pith papers cite this work. Polarity classification is still indexing.
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Pith papers citing it
years
2026 2verdicts
UNVERDICTED 2representative citing papers
A DSL lets hardware protocols be specified as imperative programs usable for both driving designs and monitoring transactions, with a tool to infer transaction traces from waveforms.
citing papers explorer
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OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design
OpenRTLSet supplies 131k+ Verilog samples with AI-generated descriptions to enable fine-tuning of LLMs for hardware module design.
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Specifying Hardware Communication as Programs
A DSL lets hardware protocols be specified as imperative programs usable for both driving designs and monitoring transactions, with a tool to infer transaction traces from waveforms.