Duet is a manycore-eFPGA architecture with cache-coherent integration that supports fine-grained acceleration and hardware augmentation, shown in RTL evaluation to cut communication latency by up to 82% and deliver 1.5-24.9x speedups on seven benchmarks.
Crossing Guard: Mediating Host-Accelerator Coherence Interactions
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jMT builds multi-execution semantics from single-execution models via causality checking to evaluate Java memory model proposals on a per-program basis and test conformance to compilers.
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jMT: Testing Correctness of Java Memory Models (Extended Version)
jMT builds multi-execution semantics from single-execution models via causality checking to evaluate Java memory model proposals on a per-program basis and test conformance to compilers.