RTL-BenchLS supplies a large-scale formally verified benchmark and three novel tasks that expose low performance of frontier LLMs on realistic RTL reasoning and generation.
Deep- RTL: Bridging verilog understanding and generation with a unified representation model
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VeriRAG is a RAG-based LLM framework that repairs Verilog RTL designs for DFT compliance using a curated dataset VeriDFT and achieves a 7.72-fold higher successful repair rate than zero-shot prompting.
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RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models
RTL-BenchLS supplies a large-scale formally verified benchmark and three novel tasks that expose low performance of frontier LLMs on realistic RTL reasoning and generation.