3DLS is a 3D-stacked architecture that physically separates KV-cache transfer traffic from tensor parallelism collectives in LLM serving, yielding up to 1.49x throughput and 60.2% lower latency.
Wsc-llm: Efficient llm service and architecture co-exploration for wafer-scale chips
2 Pith papers cite this work. Polarity classification is still indexing.
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Comprehensive profiling of expert selection in frontier MoE models reveals temporal and spatial patterns that enable 6.6x speedup on wafer-scale GPUs and 1.25x on existing systems via targeted optimizations.
citing papers explorer
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3DLS: A 3D Logic-Stacked Architecture for Disaggregated LLM Serving
3DLS is a 3D-stacked architecture that physically separates KV-cache transfer traffic from tensor parallelism collectives in LLM serving, yielding up to 1.49x throughput and 60.2% lower latency.
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Patterns behind Chaos: Forecasting Data Movement for Efficient Large-Scale MoE LLM Inference
Comprehensive profiling of expert selection in frontier MoE models reveals temporal and spatial patterns that enable 6.6x speedup on wafer-scale GPUs and 1.25x on existing systems via targeted optimizations.