FPGA emulator tests 10^13 error patterns in 20 days and diversity BP decoder matches BP+OSD logical error rates with 30-80% average speed gains and far less post-processing for QLDPC codes.
Designing fault-tolerant circuits using detector error models
2 Pith papers cite this work. Polarity classification is still indexing.
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Pith papers citing it
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quant-ph 2verdicts
UNVERDICTED 2representative citing papers
Postselection on erasure qubits fully mitigates erasure noise in QFT for erasure-check error rates below 3% and enables dual-rail systems to exceed noise floors unreachable by single-rail at kiloquop scale.
citing papers explorer
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Diversity Methods for Improving Convergence and Accuracy of Quantum Error Correction Decoders Through Hardware Emulation
FPGA emulator tests 10^13 error patterns in 20 days and diversity BP decoder matches BP+OSD logical error rates with 30-80% average speed gains and far less post-processing for QLDPC codes.
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The limits of erasure-based postselection for quantum error mitigation
Postselection on erasure qubits fully mitigates erasure noise in QFT for erasure-check error rates below 3% and enables dual-rail systems to exceed noise floors unreachable by single-rail at kiloquop scale.