Delay Monitor Circuit for Sensitive Nodes in SRAM-Based FPGA
classification
⚛️ physics.space-ph
cs.ARphysics.ins-det
keywords
circuitdelayfpgamonitornodessensitivesram-basedarchitecture
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This paper presents a novel monitor circuit architecture and experiments performed for detection of extra combinational delays in a high frequency SRAM-Based FPGA on delay sensitive nodes due to transient ionizing radiation.
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